--- a/modules/il.tp	Mon Aug 26 20:42:20 2013 -0700
+++ b/modules/il.tp	Mon Aug 26 21:04:44 2013 -0700
@@ -17,6 +17,7 @@
 	_call   <- 13
 	_ret    <- 14
 	_skipif <- 15
+	_save   <- 16
 
 	_names <- #[
 		"add"
@@ -35,6 +36,7 @@
 		"call"
 		"ret"
 		"skipIf"
+		"save"
 	]
 
 	op3:a:b:out:size <- :_opcode :_ina :_inb :_out :_size {
@@ -394,6 +396,20 @@
 				}
 			}
 		}
+		save <- :regs :scope{
+			#{
+				opcode <- { _save }
+				numops <- { 0 }
+				name <- { _names get: _save }
+				string <- {
+					block <- scope join: "\n\t"
+					if: (scope length) > 0 {
+						block <- "\n\t" . block . "\n"
+					}
+					name . " " . (regs join: " ") . " {" . block . "}"
+				}
+			}
+		}
 
 		allocRegs:withSource <- :instarr:regSrc {
 			_regMap <- dict linear
@@ -524,10 +540,15 @@
 				print: (string: reg) . " = " . assign . "\n"
 			}
 
-			//TODO: Save callee saved regs
-			map: instarr :inst {
+			withassign <- map: instarr :inst {
 				inst assignRegs: _assignments withSource: regSrc
 			}
+			psave <- regSrc needSaveProlog
+			print: "Regs that need saving in prolog: " . (psave join: ",") . "\n"
+			if: (psave length) > 0 {
+				withassign <- #[save: psave withassign]
+			}
+			withassign
 		}
 
 		//used to convert IL to a format suitable for a 2-operand architecture

--- a/modules/x86.tp	Mon Aug 26 20:42:20 2013 -0700
+++ b/modules/x86.tp	Mon Aug 26 21:04:44 2013 -0700
@@ -518,7 +518,7 @@
 					regs <- reglists get: curlist
 					len <- regs length
 					while: { found < 0 && cur < len } do: {
-						bit <- lshift: 1 by: cur
+						bit <- lshift: 1 by: ((regs get: cur) num)
 						if: (_used and bit) = 0 {
 							found <- cur
 							foundlist <- regs
@@ -586,7 +586,8 @@
 				needSaveProlog <- {
 					retval <- #[]
 					foreach: _calleesave :idx reg {
-						if: (_usedAllTime and (lshift: 1 by: (reg num))) != 0 {
+						bit <- lshift: 1 by: (reg num)
+						if: (_usedAllTime and bit) != 0 {
 							retval append: reg
 						}
 					}