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annotate jagcpu_x86.c @ 1483:001120e91fed nuklear_ui

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Skip loading menu ROM if Nuklear UI is enabled. Allow disabling Nuklear UI in favor of old menu ROM both at compile time and in config. Fall back to ROM UI if GL is unavailable
author Michael Pavone <pavone@retrodev.com>
date Sat, 25 Nov 2017 20:43:20 -0800
parents c1e78a101912
children 137dbd05ceab
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
1115
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1 #include <stdint.h>
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2 #include "backend.h"
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3 #include "jagcpu.h"
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4 #include "gen_x86.h"
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5
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6 void jag_check_resultwrite(jag_cpu_options *opts, uint8_t src, uint8_t dst)
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7 {
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8 code_info *code = &opts->gen.code;
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9 cmp_ir(code, JAGCPU_NOREG, opts->resultreg, SZ_B);
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10 code_ptr no_result = code->cur + 1;
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11 jcc(code, CC_Z, no_result + 1);
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12 //save result to current bank
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13 movzx_rr(code, opts->resultreg, opts->scratch1, SZ_B, SZ_D);
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14 mov_rrindex(code, opts->result, opts->bankptr, opts->scratch1, 4, SZ_D);
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15
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16 code_ptr writeback_penatly;
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17 if (dst == src) {
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18 //unclear if src and dst read can share a port if it's the same register
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19 //assume that is the case for now
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20 writeback_penalty = NULL;
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21 } else {
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22 cmp_ir(code, JAGCPU_NOREG, opts->writeback, SZ_B);
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23 code_ptr no_writeback_penalty = code->cur + 1;
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24 jcc(code, CC_Z, no_writeback_penalty + 1);
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25 cmp_ir(code, src, opts->writeback, SZ_B);
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26 code_ptr no_writeback_penalty2 = code->cur + 1;
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27 jcc(code, CC_Z, no_writeback_penalty2 + 1);
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28 cmp_ir(code, dst, opts->writeback, SZ_B);
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29 writeback_penalty = code->cur + 1;
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30 jcc(code, CC_NZ, writeback_penalty + 1);
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31 *no_writeback_penalty = code->cur - (no_writeback_penalty + 1);
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32 *no_writeback_penalty2 = code->cur - (no_writeback_penalty2 + 1);
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33 }
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34 cmp_ir(code, src, opts->resultreg, SZ_B);
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35 code_ptr no_result_penalty;
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36 if (dst == src) {
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37 no_result_penalty = code->cur+1;
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38 jcc(code, CC_NZ, no_result_penalty+1);
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39 } else {
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40 code_ptr result_penalty = code->cur + 1;
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41 jcc(code, CC_Z, result_penalty+1);
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42 cmp_ir(code, dst, opts->resultreg, SZ_B);
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43 no_result_penalty = code->cur+1;
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44 jcc(code, CC_NZ, no_result_penalty+1);
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45 *result_penalty = code->cur - (result_penalty + 1);
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46 }
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47 code_ptr penalty = code->cur;
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48 cycles(code, 1);
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49 *no_result_penalty = code->cur - (no_result_penalty + 1);
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50 code_ptr end = code->cur + 1;
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51 jmp(end + 1);
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52 //No result to save, but there could still be a writeback, source read conflict
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53 code_ptr end2 = NULL;
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54
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55 cmp_ir(code, JAGCPU_NOREG, opts->writeback, SZ_B);
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56 code_ptr no_resultreg_move = code->cur + 1;
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57 jcc(code, CC_Z, no_resultreg_move+1);
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58
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59 if (src != dst) {
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60 //unclear if src and dst read can share a port if it's the same register
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61 //assume that is the case for now
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62 cmp_ir(code, src, opts->writeback, SZ_B);
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63 end2 = code->cur + 1;
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64 jcc(code, CC_Z, end2+1);
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65 cmp_ir(code, src, opts->writeback, SZ_B);
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66 jcc(code, CC_NZ, penalty)
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67 }
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68 *end = code->cur - (end + 1);
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69 if (end2) {
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70 *end2 = code->cur - (end2 + 1);
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71 }
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72 *no_result = code->cur - (no_result + 1);
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73 mov_rr(code, opts->resultreg, opts->writeback, SZ_B);
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74 *no_resultreg_move = code->cur - (no_resultreg_move + 1);
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75 }
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76
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77 void jag_check_resultwrite_noread(jag_cpu_options *opts)
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78 {
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79 code_info *code = &opts->gen.code;
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80 cmp_ir(code, JAGCPU_NOREG, opts->resultreg, SZ_B);
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81 code_ptr no_result = code->cur + 1;
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82 jcc(code, CC_Z, no_result + 1);
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83 //save result to current bank
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84 movzx_rr(code, opts->resultreg, opts->scratch1, SZ_B, SZ_D);
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85 mov_rrindex(code, opts->result, opts->bankptr, opts->scratch1, 4, SZ_D);
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86 *no_result = code->cur - (no_result + 1);
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87 mov_rr(code, opts->resultreg, opts->writeback, SZ_B);
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88 }
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89
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90 void jag_check_resultwrite_singleread(jag_cpu options *opts, uint8_t reg)
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91 {
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92 code_info *code = &opts->gen.code;
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93 cmp_ir(code, JAGCPU_NOREG, opts->resultreg, SZ_B);
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94 code_ptr no_result = code->cur + 1;
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95 jcc(code, CC_Z, no_result + 1);
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96 //save result to current bank
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97 movzx_rr(code, opts->resultreg, opts->scratch1, SZ_B, SZ_D);
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98 mov_rrindex(code, opts->result, opts->bankptr, opts->scratch1, 4, SZ_D);
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99
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100 //check for a scoreboard delay
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101 cmp_ir(code, reg, opts->resultreg, SZ_B);
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102 code_ptr no_delay = code-.cur + 1;
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103 jcc(code, CC_NZ, no_delay + 1);
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104 ccylces(code, 1);
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105 *no_delay = code->cur - (no_delay = 1);
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106 *no_result = code->cur - (no_result + 1);
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107 mov_rr(code, opts->resultreg, opts->writeback, SZ_B);
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108 }
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109
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110 void translate_jag_quickimmed(jag_cpu_options *opts, uint32_t address, uint16_t opcode, uint32_t value, uint16_t dest)
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111 {
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112 jag_check_resultwrite_singleread(opts, dest);
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113 switch (opcode)
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114 {
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115 case ADDQ:
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116 break;
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117 case ADDQT:
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118 break;
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119 }
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120 }
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121
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122
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123 uint16_t *translate_jag_inst(uint16_t *stream, jag_cpu_options *opts, uint32_t address)
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124 {
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125 uint16_t inst = *stream
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126 ++stream;
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127 uint16_t opcode = jag_opcode(inst, opts->is_gpu);
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128 check_cycles_int(&opts->gen, address);
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129 code_info *code = &opts->gen.code;
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130 switch (opcode)
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131 {
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132 case JAG_MOVEI: {
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133 uint32_t value = *stream;
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134 ++stream;
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135 value |= *stream << 16;
c1e78a101912 WIP Jaguar GPU/DSP emulation
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parents:
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136 ++stream;
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
137
c1e78a101912 WIP Jaguar GPU/DSP emulation
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138 jag_check_resultwrite_noread(opts);
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
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139 mov_ir(code, value, opts->result, SZ_D);
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
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140 mov_ir(code, jag_reg2(inst), opts->resultreg, SZ_B);
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
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141 break;
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
142 }
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
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diff changeset
143 case JAG_MOVE: {
c1e78a101912 WIP Jaguar GPU/DSP emulation
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144 uint8_t src = jag_reg1(inst), dst = jag_reg2(inst);
c1e78a101912 WIP Jaguar GPU/DSP emulation
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parents:
diff changeset
145 jag_check_resultwrite_singleread(opts, src);
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
146 //move has a shorter pipeline than normal instructions
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
147 if (src != dst) {
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
148 mov_rdispr(code, opts->bankptr, src * 4, opts->gen.scratch1, SZ_D);
c1e78a101912 WIP Jaguar GPU/DSP emulation
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parents:
diff changeset
149 mov_rrdisp(code, opts->gen.scratch1, opts->bankptr, dst * 4, SZ_D);
c1e78a101912 WIP Jaguar GPU/DSP emulation
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parents:
diff changeset
150 }
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
151 mov_ir(code, dst, opts->writeback, SZ_B);
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
152 mov_ir(code, JAGCPU_NOREG, opts->resultreg, SZ_B);
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
153 break;
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
154 }
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
155 case JAG_MOVEQ: {
c1e78a101912 WIP Jaguar GPU/DSP emulation
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parents:
diff changeset
156 uint8_t dst = jag_reg2(inst);
c1e78a101912 WIP Jaguar GPU/DSP emulation
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parents:
diff changeset
157 jag_check_resultwrite_noread(opts);
c1e78a101912 WIP Jaguar GPU/DSP emulation
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diff changeset
158 //moveq has a shorter pipeline than normal instructions
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
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diff changeset
159 mov_irdisp(code, jag_quick(inst), opts->bankptr, dst * 4, SZ_D);
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
160 mov_ir(code, dst, opts->writeback, SZ_B);
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
161 mov_ir(code, JAGCPU_NOREG, opts->resultreg, SZ_B);
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
162 }
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
163 break;
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
164 case JAG_JR: {
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
165 jag_check_resultwrite_noread(opts);
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
166 //TODO: Pipeline stalls on flag readiness
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
167 uint16_t cond = jag_reg2(inst);
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
168 if (jag_is_always_false(cond)) {
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
169 } else {
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
170 int32_t offset = jag_quick(inst);
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
171 if (offset & 0x10) {
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
172 offset = -16 + (offset & 0xF);
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
173 }
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
174 }
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
175
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
176 }
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
177 break;
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
178 default:
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
179 if (is_quick_1_32_opcode(opcode, opts->is_gpu)) {
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
180 translate_jag_quickimmed(opts, address, jag_quick(inst), jag_reg2(inst));
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
181 } else if (is_quick_0_31_opcode(opcode)) {
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
182 translate_jag_quickimmed(opts, address, jag_reg1(inst), jag_reg2(inst));
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
183 } else if (is_single_source(opcode, opts->is_gpu)) {
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
184 translate_jag_single_source(opts, address, jag_reg2(isnt));
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
185 } else {
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
186 translate_jag_normal(opts, address, jag_reg1(inst), jag_reg2(inst));
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
187 }
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
188 }
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
189 return stream;
c1e78a101912 WIP Jaguar GPU/DSP emulation
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
190 }