annotate fib.s68 @ 572:0f32f52fc98e

Make some small changes in trans so that it is more likely to produce the same output as mustrans when given misbehaving programs. Add lea to testcases.txt. Improve the output of comparetest.py so that known issues can easily be separated from new ones.
author Michael Pavone <pavone@retrodev.com>
date Mon, 03 Mar 2014 21:08:43 -0800
parents f664eeb55cb4
children 2455662378ed f7fe240a7da6
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address
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1 dc.l $0, start
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address
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2 start:
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f664eeb55cb4 Mostly broken VDP core and savestate viewer
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3 moveq #36, d0
0
2432d177e1ac Initial work on M68K instruction decoding
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4 bsr fib
2432d177e1ac Initial work on M68K instruction decoding
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5 illegal
2432d177e1ac Initial work on M68K instruction decoding
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6 fib:
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5a2c1da6dd0f Make sure all operations are long-word length on fib example.
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7 cmp.l #2, d0
0
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8 blt base
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5a2c1da6dd0f Make sure all operations are long-word length on fib example.
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9 subq.l #1, d0
0
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10 move.l d0, -(a7)
2432d177e1ac Initial work on M68K instruction decoding
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11 bsr fib
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12 move.l (a7), d1
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13 exg d0, d1
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14 move.l d1, (a7)
1
5a2c1da6dd0f Make sure all operations are long-word length on fib example.
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15 subq.l #1, d0
0
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16 bsr fib
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17 move.l (a7)+, d1
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18 add.l d1, d0
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19 rts
2432d177e1ac Initial work on M68K instruction decoding
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20 base:
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21 moveq #1, d0
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22 rts