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Make the PSG and YM2612 use the master clock internal with an increment based on clock divider so that they stay perflectly in sync. Run both the PSG and YM2612 whenver one of them needs to be run.
author Mike Pavone <pavone@retrodev.com>
date Mon, 03 Jun 2013 21:43:38 -0700
parents 0ae589d4c3f9
children
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1 cmp.w <ea>, Dn 4(1/0) + <ea> time
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2 cmp.l <ea>, Dn 6(1/0) + <ea> time
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3 cmp.w #num, Dn 4(1/0) + 4(1/0)
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4 cmp.l #num, Dn 6(1/0) + 8(2/0)
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5
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6 cmpi.w #num, Dn 8(2/0)
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7 cmpi.l #num, Dn 14(3/0)
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8
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9
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10 movem
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11
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12 subtype field (bits 9-11) = 110 or 100 depending on direction
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13 bit 8 = 0
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14 bit 7 = 1
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15 bit 6 = size
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19 x86-64 registers in 68K core
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21 1. native stack pointer
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22 2. current cycle count
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23 3. target cycle count
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24 4. cartridge address
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25 5. work ram address
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26 6. scratch register
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27 7. context pointer (contains 68K registers and memory pointers not in registers)
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28 8. status register (maybe, depends on how well I can abuse native x86 status stuff)
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29 Rest of registers used for holding 68K registers
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30
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31 rax = cycle counter
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32 bl = N flag
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33 bh = V flag
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34 rcx = scratch register
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35 dl = Z flag
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36 dh = C flag
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37 rbp = target cycle count
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38 rsi = context pointer
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39 rdi = scratch register
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40 r8 = cartridge address
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41 r9 = work ram address
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42 r10 = d0
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43 r11 = d1
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44 r12 = d2
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45 r13 = a0
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46 r14 = a1
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47 r15 = a7
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48 rsp = native stack pointer
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49
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50 68K context:
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51 uint8_t flags[5];
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52 uint8_t pad??[3]
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53 uint32_t dregs[8]; //8 + 4 * reg
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54 uint32_t aregs[8]; //40 + 4 * reg
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55 .....
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56
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57 x86-64 registers in Z80 core
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58
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59 ax = HL
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60 bx = BC
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61 cx = DE
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62 dx = IX
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63 ebp = current cycle count
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64 rsi = context pointer
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65 edi = target cycle count
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66 rsp = native stack pointer
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67 r8 = IY
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68 r9 = SP
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69 r10 = A (maybe AF?)
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70 r11 = z80 ram address
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71 r12 = cartridge address if bank is pointed at ROM
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72 r13 = scratch1
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73 r14 = scratch2
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74 r15 = ?maybe z80 bank register?
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