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annotate ym2612.c @ 345:29d2ca563499

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Don't sync the 68K clock to the VDP clock unless the 68K had to wait for the VDP. This unfortunately breaks the direct color DMA demos, but should be more correct overall.
author Mike Pavone <pavone@retrodev.com>
date Sun, 19 May 2013 13:47:47 -0700
parents a8ee7934a1f8
children cc39629e8d06
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1 #include <string.h>
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2 #include "ym2612.h"
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3
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4 #define BUSY_CYCLES 17
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5 #define TIMERA_UPDATE_PERIOD 144
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6
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7 #define REG_TIMERA_HIGH 0x3 // 0x24
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8 #define REG_TIMERA_LOW 0x4 // 0x25
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9 #define REG_TIMERB 0x5 // 0x26
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10 #define REG_TIME_CTRL 0x6 // 0x27
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11
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12 #define BIT_TIMERA_ENABLE 0x1
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13 #define BIT_TIMERB_ENABLE 0x2
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14 #define BIT_TIMERA_OVEREN 0x4
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15 #define BIT_TIMERB_OVEREN 0x8
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16 #define BIT_TIMERA_RESET 0x10
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17 #define BIT_TIMERB_RESET 0x20
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18
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19 #define BIT_STATUS_TIMERA 0x1
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20 #define BIT_STATUS_TIMERB 0x2
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21
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22 void ym_init(ym2612_context * context)
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23 {
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24 memset(context, 0, sizeof(*context));
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25 }
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26
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27 void ym_run(ym2612_context * context, uint32_t to_cycle)
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28 {
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29 uint32_t delta = to_cycle - context->current_cycle;
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30 //Timers won't be perfect with this, but it's good enough for now
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31 //once actual FM emulation is in place the timers should just be
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32 //decremented/reloaded on the appropriate ticks
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33 uint32_t timer_delta = to_cycle / TIMERA_UPDATE_PERIOD;
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34 if (context->part1_regs[REG_TIME_CTRL] & BIT_TIMERA_ENABLE) {
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35 if (timer_delta > context->timer_a) {
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36 if (context->part1_regs[REG_TIME_CTRL] & BIT_TIMERA_OVEREN) {
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37 context->status |= BIT_STATUS_TIMERA;
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38 }
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39 uint32_t rem_delta = timer_delta - (context->timer_a+1);
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40 uint16_t timer_val = (context->part1_regs[REG_TIMERA_HIGH] << 2) | (context->part1_regs[REG_TIMERA_LOW] & 0x3);
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41 context->timer_a = timer_val - (rem_delta % (timer_val + 1));
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42 } else {
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43 context->timer_a -= timer_delta;
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44 }
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45 }
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46 timer_delta /= 16; //Timer B runs at 1/16th the speed of Timer A
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47 if (context->part1_regs[REG_TIME_CTRL] & BIT_TIMERB_ENABLE) {
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48 if (timer_delta > context->timer_b) {
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49 if (context->part1_regs[REG_TIME_CTRL] & BIT_TIMERB_OVEREN) {
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50 context->status |= BIT_STATUS_TIMERB;
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51 }
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52 uint32_t rem_delta = timer_delta - (context->timer_b+1);
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53 uint8_t timer_val = context->part1_regs[REG_TIMERB];
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54 context->timer_b = timer_val - (rem_delta % (timer_val + 1));
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55 } else {
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56 context->timer_a -= timer_delta;
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57 }
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58 }
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59 context->current_cycle = to_cycle;
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60 if (to_cycle >= context->write_cycle + BUSY_CYCLES) {
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61 context->status &= 0x7F;
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62 }
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63 }
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64
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65 void ym_address_write_part1(ym2612_context * context, uint8_t address)
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66 {
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67 if (address >= 0x21 && address < 0xB7) {
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68 context->selected_reg = context->part1_regs + address - 0x21;
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69 } else {
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70 context->selected_reg = NULL;
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71 }
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72 }
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73
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74 void ym_address_write_part2(ym2612_context * context, uint8_t address)
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75 {
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76 if (address >= 0x30 && address < 0xB7) {
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77 context->selected_reg = context->part1_regs + address - 0x30;
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78 } else {
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79 context->selected_reg = NULL;
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80 }
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81 }
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82
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83 void ym_data_write(ym2612_context * context, uint8_t value)
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84 {
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85 if (context->selected_reg && !(context->status & 0x80)) {
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86 *context->selected_reg = value;
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87 context->write_cycle = context->current_cycle;
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88 context->selected_reg = NULL;//TODO: Verify this
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89 }
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90 }
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91
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92 uint8_t ym_read_status(ym2612_context * context)
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93 {
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94 return context->status;
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95 }
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96