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annotate gentests.py @ 215:2b1c2c28b261

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Added headless flag to avoid initializing SDL and opening a window when running tests.
author Mike Pavone <pavone@retrodev.com>
date Fri, 19 Apr 2013 21:36:00 -0700
parents 9126c33cc33c
children acd29e2664c6
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
214
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1 #!/usr/bin/env python
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2
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3 def split_fields(line):
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4 parts = []
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5 while line:
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6 field,_,line = line.partition('\t')
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7 parts.append(field.strip())
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8 while line.startswith('\t'):
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9 line = line[1:]
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10 return parts
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11
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12 class Program(object):
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13 def __init__(self, instruction):
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14 self.avail_dregs = {0,1,2,3,4,5,6,7}
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15 self.avail_aregs = {0,1,2,3,4,5,6,7}
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16 instruction.consume_regs(self)
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17 self.inst = instruction
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18
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19 def name(self):
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20 return str(self.inst).replace('.', '_').replace('#', '_').replace(',', '_').replace(' ', '_').replace('(', '[').replace(')', ']')
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21
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22 def write_rom_test(self, outfile):
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23 outfile.write('\tdc.l $0, start\n')
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24 for i in xrange(0x8, 0x100, 0x4):
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25 outfile.write('\tdc.l empty_handler\n')
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26 outfile.write('\tdc.b "SEGA"\nempty_handler:\n\trte\nstart:\n')
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27 outfile.write('\tmove #0, CCR\n')
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28 already = {}
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29 self.inst.write_init(outfile, already)
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30 if 'label' in already:
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31 outfile.write('lbl_' + str(already['label']) + ':\n')
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32 outfile.write('\t'+str(self.inst)+'\n')
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33 outfile.write('\t'+self.inst.save_result(self.get_dreg(), True) + '\n')
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34 save_ccr = self.get_dreg()
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35 outfile.write('\tmove SR, ' + str(save_ccr) + '\n')
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36 outfile.write('\tmove #$1F, CCR\n')
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37 self.inst.invalidate_dest(already)
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38 self.inst.write_init(outfile, already)
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39 if 'label' in already:
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40 outfile.write('lbl_' + str(already['label']) + ':\n')
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41 outfile.write('\t'+str(self.inst)+'\n')
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42 outfile.write('\t'+self.inst.save_result(self.get_dreg(), False) + '\n')
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43 outfile.write('\treset\n')
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44
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45 def consume_dreg(self, num):
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46 self.avail_dregs.discard(num)
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47
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48 def consume_areg(self, num):
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49 self.avail_aregs.discard(num)
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50
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51 def get_dreg(self):
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52 return Register('d', self.avail_dregs.pop())
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53
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54 class Register(object):
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55 def __init__(self, kind, num):
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56 self.kind = kind
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57 self.num = num
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58
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59 def __str__(self):
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60 if self.kind == 'd' or self.kind == 'a':
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61 return self.kind + str(self.num)
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62 return self.kind
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63
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64 def write_init(self, outfile, size, already):
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65 if not str(self) in already:
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66 minv,maxv = get_size_range(size)
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67 val = randint(minv,maxv)
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68 already[str(self)] = val
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69 outfile.write('\tmove.'+size+' #'+str(val)+', ' + str(self) + '\n')
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70
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71 def consume_regs(self, program):
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72 if self.kind == 'd':
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73 program.consume_dreg(self.num)
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74 elif self.kind == 'a':
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75 program.consume_areg(self.num)
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76
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77 def valid_ram_address(address, size='b'):
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78 return address >= 0xE00000 and address <= 0xFFFFFFFC and (address & 0xE00000) == 0xE00000 and (size == 'b' or not address & 1)
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79
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80 def random_ram_address(mina=0xE00000, maxa=0xFFFFFFFC):
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81 return randint(mina, maxa) | 0xE00000
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82
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83 class Indexed(object):
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84 def __init__(self, base, index, index_size, disp):
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85 self.base = base
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86 self.index = index
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87 self.index_size = index_size
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88 self.disp = disp
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89
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90 def write_init(self, outfile, size, already):
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91 if self.base.kind == 'pc':
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92 if str(self.index) in already:
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93 index = already[str(self.index)]
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94 if self.index_size == 'w':
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95 index = index & 0xFFFF
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96 #sign extend index
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97 if index & 0x8000:
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98 index -= 65536
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99 if index > -1024:
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100 index = already[str(self.index)] = randint(-32768, -1024)
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101 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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102 else:
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103 index = already[str(self.index)] = randint(-32768, -1024)
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104 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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105 num = already.get('label', 0)+1
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106 already['label'] = num
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107 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp) + ' + ' + str(index)
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108 else:
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109 if str(self.base) in already:
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110 if not valid_ram_address(already[str(self.base)]):
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111 del already[str(self.base)]
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112 self.write_init(outfile, size, already)
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113 return
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114 else:
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115 base = already[str(self.base)]
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116 else:
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117 base = already[str(self.base)] = random_ram_address()
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118 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
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119 if str(self.index) in already:
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120 index = already[str(self.index)]
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121 if self.index_size == 'w':
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122 index = index & 0xFFFF
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123 #sign extend index
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124 if index & 0x8000:
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125 index -= 65536
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126 if not valid_ram_address(base + index):
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127 index = already[str(self.index)] = randint(-64, 63)
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128 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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129 else:
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130 index = already[str(self.index)] = randint(-64, 63)
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131 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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132 address = base + index + self.disp
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133 if (address & 0xFFFFFF) < 0xE00000:
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134 if (address & 0xFFFFFF) < 128:
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135 self.disp -= (address & 0xFFFFFF)
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136 else:
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137 self.disp += 0xE00000-(address & 0xFFFFFF)
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138 address = base + index + self.disp
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139 elif (address & 0xFFFFFF) > 0xFFFFFC:
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140 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
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141 address = base + index + self.disp
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142 if size != 'b' and address & 1:
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143 self.disp = self.disp ^ 1
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144 address = base + index + self.disp
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145 minv,maxv = get_size_range(size)
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146 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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147
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148 def __str__(self):
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149 return '(' + str(self.disp) + ', ' + str(self.base) + ', ' + str(self.index) + '.' + self.index_size + ')'
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150
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diff changeset
151 def consume_regs(self, program):
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152 self.base.consume_regs(program)
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parents:
diff changeset
153 self.index.consume_regs(program)
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154
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diff changeset
155 class Displacement(object):
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156 def __init__(self, base, disp):
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157 self.base = base
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158 self.disp = disp
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parents:
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159
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parents:
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160 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
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diff changeset
161 if self.base.kind == 'pc':
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162 num = already.get('label', 0)+1
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163 already['label'] = num
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parents:
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164 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp)
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165 else:
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166 if str(self.base) in already:
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167 if not valid_ram_address(already[str(self.base)]):
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168 del already[str(self.base)]
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169 self.write_init(outfile, size, already)
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170 return
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
171 else:
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172 base = already[str(self.base)]
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173 else:
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174 base = already[str(self.base)] = random_ram_address()
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175 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
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parents:
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176 address = base + self.disp
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177 if (address & 0xFFFFFF) < 0xE00000:
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Mike Pavone <pavone@retrodev.com>
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178 if (address & 0xFFFFFF) < 0x10000:
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179 self.disp -= (address & 0xFFFFFF)
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180 else:
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181 self.disp += 0xE00000-(address & 0xFFFFFF)
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182 address = base + self.disp
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Mike Pavone <pavone@retrodev.com>
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183 elif (address & 0xFFFFFF) > 0xFFFFFC:
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184 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
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185 address = base + self.disp
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186 if size != 'b' and address & 1:
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187 self.disp = self.disp ^ 1
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188 address = base + self.disp
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189 minv,maxv = get_size_range(size)
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190 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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191
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192 def __str__(self):
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193 return '(' + str(self.disp) + ', ' + str(self.base) + ')'
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194
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195 def consume_regs(self, program):
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196 self.base.consume_regs(program)
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197
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198 class Indirect(object):
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199 def __init__(self, reg):
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200 self.reg = reg
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201
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202 def __str__(self):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
203 return '(' + str(self.reg) + ')'
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204
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diff changeset
205 def write_init(self, outfile, size, already):
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206 if str(self.reg) in already:
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parents:
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207 if not valid_ram_address(already[str(self.reg)], size):
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parents:
diff changeset
208 del already[str(self.reg)]
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diff changeset
209 self.write_init(outfile, size, already)
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parents:
diff changeset
210 return
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
211 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
212 address = already[str(self.reg)]
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parents:
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213 else:
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diff changeset
214 address = random_ram_address()
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parents:
diff changeset
215 if size != 'b':
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parents:
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216 address = address & 0xFFFFFFFE
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parents:
diff changeset
217 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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parents:
diff changeset
218 already[str(self.reg)] = address
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parents:
diff changeset
219 minv,maxv = get_size_range(size)
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parents:
diff changeset
220 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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parents:
diff changeset
221
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222 def consume_regs(self, program):
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parents:
diff changeset
223 self.reg.consume_regs(program)
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224
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225 class Increment(object):
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parents:
diff changeset
226 def __init__(self, reg):
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227 self.reg = reg
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diff changeset
228
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diff changeset
229 def __str__(self):
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parents:
diff changeset
230 return '(' + str(self.reg) + ')+'
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parents:
diff changeset
231
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parents:
diff changeset
232 def write_init(self, outfile, size, already):
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parents:
diff changeset
233 if str(self.reg) in already:
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parents:
diff changeset
234 if not valid_ram_address(already[str(self.reg)], size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
235 del already[str(self.reg)]
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parents:
diff changeset
236 self.write_init(outfile, size, already)
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parents:
diff changeset
237 return
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
238 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
239 address = already[str(self.reg)]
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parents:
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240 else:
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parents:
diff changeset
241 address = random_ram_address()
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
242 if size != 'b':
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parents:
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243 address = address & 0xFFFFFFFE
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diff changeset
244 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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parents:
diff changeset
245 already[str(self.reg)] = address
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parents:
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246 minv,maxv = get_size_range(size)
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parents:
diff changeset
247 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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parents:
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248
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diff changeset
249 def consume_regs(self, program):
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parents:
diff changeset
250 self.reg.consume_regs(program)
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251
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parents:
diff changeset
252 class Decrement(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
253 def __init__(self, reg):
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parents:
diff changeset
254 self.reg = reg
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parents:
diff changeset
255
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
256 def __str__(self):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
257 return '-(' + str(self.reg) + ')'
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parents:
diff changeset
258
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parents:
diff changeset
259 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
260 if str(self.reg) in already:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
261 if not valid_ram_address(already[str(self.reg)]- 4 if size == 'l' else 2 if size == 'w' else 1, size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
262 del already[str(self.reg)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
263 self.write_init(outfile, size, already)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
264 return
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
265 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
266 address = already[str(self.reg)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
267 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
268 address = random_ram_address(mina=0xE00004)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
269 if size != 'b':
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Mike Pavone <pavone@retrodev.com>
parents:
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270 address = address & 0xFFFFFFFE
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parents:
diff changeset
271 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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parents:
diff changeset
272 already[str(self.reg)] = address
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parents:
diff changeset
273 minv,maxv = get_size_range(size)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
274 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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parents:
diff changeset
275
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diff changeset
276 def consume_regs(self, program):
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parents:
diff changeset
277 self.reg.consume_regs(program)
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parents:
diff changeset
278
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parents:
diff changeset
279 class Absolute(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
280 def __init__(self, address, size):
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parents:
diff changeset
281 self.address = address
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
282 self.size = size
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
283
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parents:
diff changeset
284 def __str__(self):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
285 return '(' + str(self.address) + ').' + self.size
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
286
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
287 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
288 minv,maxv = get_size_range(size)
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parents:
diff changeset
289 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', '+str(self)+'\n')
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parents:
diff changeset
290
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parents:
diff changeset
291 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
292 pass
9126c33cc33c Add test generator, builder and runner
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parents:
diff changeset
293
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parents:
diff changeset
294 class Immediate(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
295 def __init__(self, value):
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parents:
diff changeset
296 self.value = value
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
297
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
298 def __str__(self):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
299 return '#' + str(self.value)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
300
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
301 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
302 pass
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
303
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
304 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
305 pass
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
306
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
307 all_dregs = [Register('d', i) for i in range(0, 8)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
308 all_aregs = [Register('a', i) for i in range(0, 8)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
309 all_indirect = [Indirect(reg) for reg in all_aregs]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
310 all_predec = [Decrement(reg) for reg in all_aregs]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
311 all_postinc = [Increment(reg) for reg in all_aregs]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
312 from random import randint
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
313 def all_indexed():
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
314 return [Indexed(base, index, index_size, randint(-128, 127)) for base in all_aregs for index in all_dregs + all_aregs for index_size in ('w','l')]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
315
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
316 def all_disp():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
317 return [Displacement(base, randint(-32768, 32767)) for base in all_aregs]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
318
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
319 def rand_pc_disp():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
320 return [Displacement(Register('pc', 0), randint(-32768, -1024)) for x in xrange(0, 8)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
321
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
322 def all_pc_indexed():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
323 return [Indexed(Register('pc', 0), index, index_size, randint(-128, 127)) for index in all_dregs + all_aregs for index_size in ('w','l')]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
324
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
325 def rand_abs_short():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
326 return [Absolute(0xFFFF8000 + randint(0, 32767), 'w') for x in xrange(0, 8)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
327
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
328 def rand_abs_long():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
329 return [Absolute(0xFF0000 + randint(0, 65535), 'l') for x in xrange(0, 8)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
330
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
331 def get_size_range(size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
332 if size == 'b':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
333 return (-128, 127)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
334 elif size == 'w':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
335 return (-32768, 32767)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
336 else:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
337 return (-2147483648, 2147483647)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
338
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
339 def rand_immediate(size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
340 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
341
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
342 return [Immediate(randint(minv, maxv)) for x in xrange(0,8)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
343
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
344 def get_variations(mode, size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
345 mapping = {
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
346 'd':all_dregs,
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
347 'a':all_aregs,
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
348 '(a)':all_indirect,
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
349 '-(a)':all_predec,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
350 '(a)+':all_postinc,
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
351 '(n,a)':all_disp,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
352 '(n,a,x)':all_indexed,
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
353 '(n,pc)':rand_pc_disp,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
354 '(n,pc,x)':all_pc_indexed,
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
355 '(n).w':rand_abs_short,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
356 '(n).l':rand_abs_long
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
357 }
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
358 if mode in mapping:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
359 ret = mapping[mode]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
360 if type(ret) != list:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
361 ret = ret()
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
362 return ret
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
363 elif mode == '#n':
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
364 return rand_immediate(size)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
365 elif mode.startswith('#(') and mode.endswith(')'):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
366 inner = mode[2:-1]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
367 start,sep,end = inner.partition('-')
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
368 return [Immediate(num) for num in range(int(start), int(end))]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
369
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
370 class Inst2Op(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
371 def __init__(self, name, size, src, dst):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
372 self.name = name
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
373 self.size = size
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
374 self.src = src
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
375 self.dst = dst
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
376
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
377 def __str__(self):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
378 return self.name + '.' + self.size + ' ' + str(self.src) + ', ' + str(self.dst)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
379
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
380 def write_init(self, outfile, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
381 self.src.write_init(outfile, self.size, already)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
382 self.dst.write_init(outfile, self.size, already)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
383
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
384 def invalidate_dest(self, already):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
385 if type(self.dst) == Register:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
386 del already[str(self.dst)]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
387
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
388 def save_result(self, reg, always):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
389 if always or type(self.dst) != Register:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
390 return 'move.' + self.size + ' ' + str(self.dst) + ', ' + str(reg)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
391 else:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
392 return ''
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
393
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
394 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
395 self.src.consume_regs(program)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
396 self.dst.consume_regs(program)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
397
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
398 class Entry(object):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
399 def __init__(self, line):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
400 fields = split_fields(line)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
401 self.name = fields[0]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
402 sizes = fields[1]
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
403 sources = fields[2].split(';')
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
404 dests = fields[3].split(';')
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
405 combos = []
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
406 for size in sizes:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
407 for source in sources:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
408 if size != 'b' or source != 'a':
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
409 for dest in dests:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
410 if size != 'b' or dest != 'a':
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
411 combos.append((size, source, dest))
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
412 self.cases = combos
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
413
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
414 def programs(self):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
415 res = []
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
416 for (size, src, dst) in self.cases:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
417 sources = get_variations(src, size)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
418 dests = get_variations(dst, size)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
419 for source in sources:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
420 for dest in dests:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
421 res.append(Program(Inst2Op(self.name, size, source, dest)))
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
422 return res
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
423
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
424 def process_entries(f):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
425 entries = []
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
426 for line in f:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
427 if not line.startswith('Name') and not line.startswith('#') and len(line.strip()) > 0:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
428 entries.append(Entry(line))
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
429 return entries
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
430
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
431
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
432 def main(args):
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
433 entries = process_entries(open('testcases.txt'))
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
434 for entry in entries:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
435 programs = entry.programs()
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
436 for program in programs:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
437 f = open('generated_tests/' + program.name() + '.s68', 'w')
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
438 program.write_rom_test(f)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
439 f.close()
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
440
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
441 if __name__ == '__main__':
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
442 import sys
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
443 main(sys.argv)
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
444