annotate gen_arm.h @ 995:2bc27415565b

Fix some stuff with interrupt timing. The change in adjust_int_cycle gets Overdrive working again (vint was not being preferred over hint in some cases). One of the changes seems to have broken Fatal Rewind again, but no other regressions that I can see.
author Michael Pavone <pavone@retrodev.com>
date Sat, 30 Apr 2016 08:37:55 -0700
parents bff307e03a94
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
553
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1 /*
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2 Copyright 2014 Michael Pavone
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3 This file is part of BlastEm.
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
5 */
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
6 #ifndef GEN_ARM_H_
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
7 #define GEN_ARM_H_
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
8
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
9 #include <stdint.h>
563
c8fefa140c80 Moved some generic stuff from backend.h gen_arm.h and gen_arm.c into gen.h and gen.c. Added a couple fields to cpu_options so that gen_mem_fun can be made guest CPU generic
Michael Pavone <pavone@retrodev.com>
parents: 553
diff changeset
10 #include "gen.h"
553
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
11
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
12 #define SET_COND 0x100000u
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
13 #define NO_COND 0u
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
14
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
15 #define CC_FIELD_SHIFT 28
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
16
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
17 #define CC_EQ 0x0u
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
18 #define CC_NE (0x1u << CC_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
19 #define CC_CS (0x2u << CC_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
20 #define CC_CC (0x3u << CC_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
21 #define CC_MI (0x4u << CC_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
22 #define CC_PL (0x5u << CC_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
23 #define CC_VS (0x6u << CC_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
24 #define CC_VC (0x7u << CC_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
25 #define CC_HI (0x8u << CC_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
26 #define CC_LS (0x9u << CC_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
27 #define CC_GE (0xAu << CC_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
28 #define CC_LT (0xBu << CC_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
29 #define CC_GT (0xCu << CC_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
30 #define CC_LE (0xDu << CC_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
31 #define CC_AL (0xEu << CC_FIELD_SHIFT)
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
32
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
33 #define INVALID_IMMED 0xFFFFFFFFu
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
34 #define CODE_OK 0u
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
35
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
36 enum {
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
37 r0,
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
38 r1,
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
39 r2,
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
40 r3,
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
41 r4,
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
42 r5,
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
43 r6,
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
44 r7,
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
45 r8,
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
46 r9,
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
47 r10,
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
48 r11,
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
49 r12,
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
50 sp,
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
51 lr,
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
52 pc
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
53 };
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
54
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
55 #define R0 0x1
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
56 #define R1 0x2
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
57 #define R2 0x4
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
58 #define R3 0x8
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
59 #define R4 0x10
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
60 #define R5 0x20
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
61 #define R6 0x40
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
62 #define R7 0x80
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
63 #define R8 0x100
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
64 #define R9 0x200
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
65 #define R10 0x400
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
66 #define R11 0x800
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
67 #define R12 0x1000
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
68 #define SP 0x2000
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
69 #define LR 0x4000
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
70 #define PC 0x8000
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
71
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
72 uint32_t and(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
73 uint32_t andi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
74 uint32_t and_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
75 uint32_t andi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
76 uint32_t eor(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
77 uint32_t eori(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
78 uint32_t eor_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
79 uint32_t eori_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
80 uint32_t sub(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
81 uint32_t subi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
82 uint32_t sub_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
83 uint32_t subi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
84 uint32_t rsb(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
85 uint32_t rsbi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
86 uint32_t rsb_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
87 uint32_t rsbi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
88 uint32_t add(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
89 uint32_t addi(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
90 uint32_t add_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
91 uint32_t addi_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
92 uint32_t adc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
93 uint32_t adci(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
94 uint32_t adc_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
95 uint32_t adci_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
96 uint32_t sbc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
97 uint32_t sbci(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
98 uint32_t sbc_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
99 uint32_t sbci_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
100 uint32_t rsc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
101 uint32_t rsci(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
102 uint32_t rsc_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
103 uint32_t rsci_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
104 uint32_t tst(code_info *code, uint32_t src1, uint32_t src2);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
105 uint32_t tsti(code_info *code, uint32_t src1, uint32_t immed);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
106 uint32_t tst_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
107 uint32_t tsti_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
108 uint32_t teq(code_info *code, uint32_t src1, uint32_t src2);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
109 uint32_t teqi(code_info *code, uint32_t src1, uint32_t immed);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
110 uint32_t teq_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
111 uint32_t teqi_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
112 uint32_t cmp(code_info *code, uint32_t src1, uint32_t src2);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
113 uint32_t cmpi(code_info *code, uint32_t src1, uint32_t immed);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
114 uint32_t cmp_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
115 uint32_t cmpi_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
116 uint32_t cmn(code_info *code, uint32_t src1, uint32_t src2);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
117 uint32_t cmni(code_info *code, uint32_t src1, uint32_t immed);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
118 uint32_t cmn_cc(code_info *code, uint32_t src1, uint32_t src2, uint32_t cc);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
119 uint32_t cmni_cc(code_info *code, uint32_t src1, uint32_t immed, uint32_t cc);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
120 uint32_t orr(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
121 uint32_t orri(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
122 uint32_t orr_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
123 uint32_t orri_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
124 uint32_t mov(code_info *code, uint32_t dst, uint32_t src2, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
125 uint32_t movi(code_info *code, uint32_t dst, uint32_t immed, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
126 uint32_t mov_cc(code_info *code, uint32_t dst, uint32_t src2, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
127 uint32_t movi_cc(code_info *code, uint32_t dst, uint32_t immed, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
128 uint32_t bic(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
129 uint32_t bici(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
130 uint32_t bic_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
131 uint32_t bici_cc(code_info *code, uint32_t dst, uint32_t src1, uint32_t immed, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
132 uint32_t mvn(code_info *code, uint32_t dst, uint32_t src2, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
133 uint32_t mvni(code_info *code, uint32_t dst, uint32_t immed, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
134 uint32_t mvn_cc(code_info *code, uint32_t dst, uint32_t src2, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
135 uint32_t mvni_cc(code_info *code, uint32_t dst, uint32_t immed, uint32_t cc, uint32_t set_cond);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
136
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
137 uint32_t b(code_info *code, uint32_t *dst);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
138 uint32_t b_cc(code_info *code, uint32_t *dst, uint32_t cc);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
139 uint32_t bl(code_info *code, uint32_t *dst);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
140 uint32_t bl_cc(code_info *code, uint32_t *dst, uint32_t cc);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
141 uint32_t bx(code_info *code, uint32_t dst);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
142 uint32_t bx_cc(code_info *code, uint32_t dst, uint32_t cc);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
143
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
144 uint32_t push(code_info *code, uint32_t reg);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
145 uint32_t push_cc(code_info *code, uint32_t reg, uint32_t cc);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
146 uint32_t pushm(code_info *code, uint32_t reglist);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
147 uint32_t pushm_cc(code_info *code, uint32_t reglist, uint32_t cc);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
148 uint32_t pop(code_info *code, uint32_t reg);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
149 uint32_t pop_cc(code_info *code, uint32_t reg, uint32_t cc);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
150 uint32_t popm(code_info *code, uint32_t reglist);
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
151 uint32_t popm_cc(code_info *code, uint32_t reglist, uint32_t cc);
684
bff307e03a94 Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents: 563
diff changeset
152 uint32_t ldr_cc(code_info *code, uint32_t dst, uint32_t base, int32_t offset, uint32_t cc);
bff307e03a94 Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents: 563
diff changeset
153 uint32_t ldr(code_info *code, uint32_t rst, uint32_t base, int32_t offset);
bff307e03a94 Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents: 563
diff changeset
154 uint32_t str_cc(code_info *code, uint32_t src, uint32_t base, int32_t offset, uint32_t cc);
bff307e03a94 Added ldr and str instructions to gen_arm
Michael Pavone <pavone@retrodev.com>
parents: 563
diff changeset
155 uint32_t str(code_info *code, uint32_t src, uint32_t base, int32_t offset);
553
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
156
1af6c1052993 Added untested code for generating ARM machine code
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
157 #endif //GEN_ARM_H_