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annotate z80_to_x86.c @ 2471:2f4c17b4fe10

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Switch to YMZ280B ADPCM algorithm. Still sounds a little rough, but definitely much better than with the YM2610 ADPCM-A setup
author Michael Pavone <pavone@retrodev.com>
date Sun, 25 Feb 2024 11:08:35 -0800
parents 767ec72acca7
children dbff641a33df
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140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
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1 /*
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2 Copyright 2013 Michael Pavone
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b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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3 This file is part of BlastEm.
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
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5 */
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6 #include "z80inst.h"
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7 #include "z80_to_x86.h"
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8 #include "gen_x86.h"
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9 #include "mem.h"
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724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
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10 #include "util.h"
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11 #include <stdio.h>
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12 #include <stdlib.h>
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13 #include <stddef.h>
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14 #include <string.h>
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15
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16 #define MODE_UNUSED (MODE_IMMED-1)
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17 #define MAX_MCYCLE_LENGTH 6
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18 #define NATIVE_CHUNK_SIZE 1024
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19 #define NATIVE_MAP_CHUNKS (0x10000 / NATIVE_CHUNK_SIZE)
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20
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21 //#define DO_DEBUG_PRINT
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22
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23 #ifdef DO_DEBUG_PRINT
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24 #define dprintf printf
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25 #else
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26 #define dprintf
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27 #endif
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28
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29 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst);
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30 void z80_handle_deferred(z80_context * context);
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31
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32 uint8_t z80_size(z80inst * inst)
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33 {
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34 uint8_t reg = (inst->reg & 0x1F);
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35 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) {
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36 return reg < Z80_BC ? SZ_B : SZ_W;
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37 }
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38 //TODO: Handle any necessary special cases
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39 return SZ_B;
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40 }
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41
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42 uint8_t zf_off(uint8_t flag)
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43 {
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44 return offsetof(z80_context, flags) + flag;
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45 }
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46
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47 uint8_t zaf_off(uint8_t flag)
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48 {
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49 return offsetof(z80_context, alt_flags) + flag;
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50 }
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51
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52 uint8_t zr_off(uint8_t reg)
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53 {
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54 if (reg > Z80_A) {
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55 reg = z80_low_reg(reg);
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56 }
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57 return offsetof(z80_context, regs) + reg;
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58 }
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59
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60 uint8_t zar_off(uint8_t reg)
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61 {
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62 if (reg > Z80_A) {
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63 reg = z80_low_reg(reg);
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64 }
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65 return offsetof(z80_context, alt_regs) + reg;
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66 }
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67
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68 void zreg_to_native(z80_options *opts, uint8_t reg, uint8_t native_reg)
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69 {
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70 if (opts->regs[reg] >= 0) {
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71 mov_rr(&opts->gen.code, opts->regs[reg], native_reg, reg > Z80_A ? SZ_W : SZ_B);
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72 } else {
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73 mov_rdispr(&opts->gen.code, opts->gen.context_reg, zr_off(reg), native_reg, reg > Z80_A ? SZ_W : SZ_B);
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74 }
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75 }
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76
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77 void native_to_zreg(z80_options *opts, uint8_t native_reg, uint8_t reg)
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78 {
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79 if (opts->regs[reg] >= 0) {
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80 mov_rr(&opts->gen.code, native_reg, opts->regs[reg], reg > Z80_A ? SZ_W : SZ_B);
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81 } else {
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82 mov_rrdisp(&opts->gen.code, native_reg, opts->gen.context_reg, zr_off(reg), reg > Z80_A ? SZ_W : SZ_B);
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83 }
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84 }
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85
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86 void translate_z80_reg(z80inst * inst, host_ea * ea, z80_options * opts)
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87 {
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88 code_info *code = &opts->gen.code;
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89 if (inst->reg == Z80_USE_IMMED) {
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90 ea->mode = MODE_IMMED;
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91 ea->disp = inst->immed;
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92 } else if ((inst->reg & 0x1F) == Z80_UNUSED) {
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93 ea->mode = MODE_UNUSED;
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94 } else {
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95 ea->mode = MODE_REG_DIRECT;
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96 if (inst->reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
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97 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
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98 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W);
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99 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
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100 ea->base = opts->gen.scratch1;
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101 } else {
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102 ea->base = opts->regs[Z80_IYL];
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103 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
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104 }
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105 } else if(opts->regs[inst->reg] >= 0) {
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106 ea->base = opts->regs[inst->reg];
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107 if (ea->base >= AH && ea->base <= BH) {
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108 if ((inst->addr_mode & 0x1F) == Z80_REG) {
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109 uint8_t other_reg = opts->regs[inst->ea_reg];
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110 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) {
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111 //we can't mix an *H reg with a register that requires the REX prefix
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112 ea->base = opts->regs[z80_low_reg(inst->reg)];
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113 ror_ir(code, 8, ea->base, SZ_W);
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114 }
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115 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
116 //temp regs require REX prefix too
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
117 ea->base = opts->regs[z80_low_reg(inst->reg)];
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
118 ror_ir(code, 8, ea->base, SZ_W);
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
119 }
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
120 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
121 } else {
262
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
122 ea->mode = MODE_REG_DISPLACE8;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
123 ea->base = opts->gen.context_reg;
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
124 ea->disp = zr_off(inst->reg);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
125 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
126 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
127 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
128
590
ea80559c67cb WIP effort to update z80 core for code gen changes
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parents: 506
diff changeset
129 void z80_save_reg(z80inst * inst, z80_options * opts)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
130 {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
131 code_info *code = &opts->gen.code;
716
b707a8ddc202 Make sure z80_save_reg does nothing when there is no register in the reg field of the instruction. This fixes a bug that corrupted SP in the MDEM 2011 demo
Michael Pavone <pavone@retrodev.com>
parents: 715
diff changeset
132 if (inst->reg == Z80_USE_IMMED || inst->reg == Z80_UNUSED) {
b707a8ddc202 Make sure z80_save_reg does nothing when there is no register in the reg field of the instruction. This fixes a bug that corrupted SP in the MDEM 2011 demo
Michael Pavone <pavone@retrodev.com>
parents: 715
diff changeset
133 return;
b707a8ddc202 Make sure z80_save_reg does nothing when there is no register in the reg field of the instruction. This fixes a bug that corrupted SP in the MDEM 2011 demo
Michael Pavone <pavone@retrodev.com>
parents: 715
diff changeset
134 }
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
135 if (inst->reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
136 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
137 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
138 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
139 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
140 } else {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
141 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
142 }
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
143 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
144 if ((inst->addr_mode & 0x1F) == Z80_REG) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
145 uint8_t other_reg = opts->regs[inst->ea_reg];
269
3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX.
Mike Pavone <pavone@retrodev.com>
parents: 268
diff changeset
146 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) {
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
147 //we can't mix an *H reg with a register that requires the REX prefix
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
148 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
268
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
149 }
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
150 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents: 267
diff changeset
151 //temp regs require REX prefix too
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
152 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
153 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
154 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
155 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
156
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
157 void translate_z80_ea(z80inst * inst, host_ea * ea, z80_options * opts, uint8_t read, uint8_t modify)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
158 {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
159 code_info *code = &opts->gen.code;
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
160 uint8_t size, areg;
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
161 int8_t reg;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
162 ea->mode = MODE_REG_DIRECT;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
163 areg = read ? opts->gen.scratch1 : opts->gen.scratch2;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
164 switch(inst->addr_mode & 0x1F)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
165 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
166 case Z80_REG:
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
167 if (inst->ea_reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
168 if (inst->reg == Z80_IYL) {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
169 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
170 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
171 ea->base = opts->gen.scratch1;
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
172 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
173 ea->base = opts->regs[Z80_IYL];
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
174 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
175 }
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
176 } else if(opts->regs[inst->ea_reg] >= 0) {
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
177 ea->base = opts->regs[inst->ea_reg];
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
178 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) {
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
179 uint8_t other_reg = opts->regs[inst->reg];
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
180 #ifdef X86_64
269
3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX.
Mike Pavone <pavone@retrodev.com>
parents: 268
diff changeset
181 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) {
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
182 //we can't mix an *H reg with a register that requires the REX prefix
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
183 ea->base = opts->regs[z80_low_reg(inst->ea_reg)];
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
184 ror_ir(code, 8, ea->base, SZ_W);
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
185 }
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
186 #endif
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
187 }
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
188 } else {
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
189 ea->mode = MODE_REG_DISPLACE8;
659
759c38bf97f8 Minor Z80 core cleanup
Michael Pavone <pavone@retrodev.com>
parents: 657
diff changeset
190 ea->base = opts->gen.context_reg;
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
191 ea->disp = zr_off(inst->ea_reg);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
192 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
193 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
194 case Z80_REG_INDIRECT:
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
195 zreg_to_native(opts, inst->ea_reg, areg);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
196 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
197 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
198 if (modify) {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
199 //push_r(code, opts->gen.scratch1);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
200 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
201 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
202 if (size == SZ_B) {
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
203 call(code, opts->read_8);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
204 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
205 call(code, opts->read_16);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
206 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
207 }
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
208 ea->base = opts->gen.scratch1;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
209 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
210 case Z80_IMMED:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
211 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
212 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
213 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
214 case Z80_IMMED_INDIRECT:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
215 mov_ir(code, inst->immed, areg, SZ_W);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
216 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
217 if (read) {
277
765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller
Mike Pavone <pavone@retrodev.com>
parents: 275
diff changeset
218 /*if (modify) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
219 push_r(code, opts->gen.scratch1);
277
765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller
Mike Pavone <pavone@retrodev.com>
parents: 275
diff changeset
220 }*/
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
221 if (size == SZ_B) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
222 call(code, opts->read_8);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
223 } else {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
224 call(code, opts->read_16);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
225 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
226 }
590
ea80559c67cb WIP effort to update z80 core for code gen changes
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parents: 506
diff changeset
227 ea->base = opts->gen.scratch1;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
228 break;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
229 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
230 case Z80_IY_DISPLACE:
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
231 zreg_to_native(opts, (inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY, areg);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
232 add_ir(code, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
233 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
234 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
235 if (modify) {
591
966b46c68942 Get Z80 core back into compileable state
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parents: 590
diff changeset
236 //push_r(code, opts->gen.scratch1);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
237 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
238 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
239 if (size == SZ_B) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
240 call(code, opts->read_8);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
241 } else {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
242 call(code, opts->read_16);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
243 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
244 }
590
ea80559c67cb WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents: 506
diff changeset
245 ea->base = opts->gen.scratch1;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
246 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
247 case Z80_UNUSED:
235
d9bf8e61c33c Get Z80 core working for simple programs
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parents: 213
diff changeset
248 ea->mode = MODE_UNUSED;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
249 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
250 default:
792
724bbec47f86 Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents: 755
diff changeset
251 fatal_error("Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
252 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
253 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
254
591
966b46c68942 Get Z80 core back into compileable state
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parents: 590
diff changeset
255 void z80_save_ea(code_info *code, z80inst * inst, z80_options * opts)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
256 {
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
257 if ((inst->addr_mode & 0x1F) == Z80_REG) {
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
258 if (inst->ea_reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) {
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
259 if (inst->reg == Z80_IYL) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
260 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
261 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
262 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
263 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
264 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL
Mike Pavone <pavone@retrodev.com>
parents: 311
diff changeset
265 }
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
266 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
267 uint8_t other_reg = opts->regs[inst->reg];
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
268 #ifdef X86_64
269
3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX.
Mike Pavone <pavone@retrodev.com>
parents: 268
diff changeset
269 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) {
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
270 //we can't mix an *H reg with a register that requires the REX prefix
591
966b46c68942 Get Z80 core back into compileable state
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parents: 590
diff changeset
271 ror_ir(code, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W);
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
272 }
666
b68039895627 In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents: 665
diff changeset
273 #endif
267
1788e3f29c28 Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents: 266
diff changeset
274 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
275 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
276 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
277
593
5ef3fe516da9 Z80 core is sort of working again
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parents: 592
diff changeset
278 void z80_save_result(z80_options *opts, z80inst * inst)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
279 {
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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parents: 252
diff changeset
280 switch(inst->addr_mode & 0x1f)
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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parents: 252
diff changeset
281 {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
282 case Z80_REG_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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parents: 252
diff changeset
283 case Z80_IMMED_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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parents: 252
diff changeset
284 case Z80_IX_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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parents: 252
diff changeset
285 case Z80_IY_DISPLACE:
1045
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
286 if (inst->op != Z80_LD) {
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
287 mov_rdispr(&opts->gen.code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W);
e0489abfdab0 Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents: 1044
diff changeset
288 }
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
289 if (z80_size(inst) == SZ_B) {
593
5ef3fe516da9 Z80 core is sort of working again
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parents: 592
diff changeset
290 call(&opts->gen.code, opts->write_8);
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
291 } else {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
292 call(&opts->gen.code, opts->write_16_lowfirst);
253
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents: 252
diff changeset
293 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
294 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
295 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
296
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
297 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
298 DONT_READ=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
299 READ
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
300 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
301
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
302 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
303 DONT_MODIFY=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
304 MODIFY
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
305 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
306
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
307 void z80_print_regs_exit(z80_context * context)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
308 {
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
309 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n",
235
d9bf8e61c33c Get Z80 core working for simple programs
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parents: 213
diff changeset
310 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C],
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
311 context->regs[Z80_D], context->regs[Z80_E],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
312 (context->regs[Z80_H] << 8) | context->regs[Z80_L],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
313 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
314 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL],
243
2f069a0b487e Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 242
diff changeset
315 context->sp, context->im, context->iff1, context->iff2);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
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parents: 239
diff changeset
316 puts("--Alternate Regs--");
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
317 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n",
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
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parents: 239
diff changeset
318 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C],
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
319 context->alt_regs[Z80_D], context->alt_regs[Z80_E],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
320 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
321 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL],
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
322 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]);
235
d9bf8e61c33c Get Z80 core working for simple programs
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parents: 213
diff changeset
323 exit(0);
d9bf8e61c33c Get Z80 core working for simple programs
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parents: 213
diff changeset
324 }
d9bf8e61c33c Get Z80 core working for simple programs
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parents: 213
diff changeset
325
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
326 void translate_z80inst(z80inst * inst, z80_context * context, uint16_t address, uint8_t interp)
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff changeset
327 {
2418
cc07f544c620 Fix uninitialized base cycle count in Z80 interp path and do a little other interp path cleanup. Fixes issue with 3x3 Eyes
Michael Pavone <pavone@retrodev.com>
parents: 2412
diff changeset
328 uint32_t num_cycles = 0;
591
966b46c68942 Get Z80 core back into compileable state
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parents: 590
diff changeset
329 host_ea src_op, dst_op;
235
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parents: 213
diff changeset
330 uint8_t size;
590
ea80559c67cb WIP effort to update z80 core for code gen changes
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parents: 506
diff changeset
331 z80_options *opts = context->options;
591
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parents: 590
diff changeset
332 uint8_t * start = opts->gen.code.cur;
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
333 code_info *code = &opts->gen.code;
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
334 if (!interp) {
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
335 check_cycles_int(&opts->gen, address);
819
ab017fb09e77 Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 792
diff changeset
336 if (context->breakpoint_flags[address / 8] & (1 << (address % 8))) {
627
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
337 zbreakpoint_patch(context, address, start);
c5820734a5b6 Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents: 626
diff changeset
338 }
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
339 num_cycles = 4 * inst->opcode_bytes;
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
340 add_ir(code, inst->opcode_bytes > 1 ? 2 : 1, opts->regs[Z80_R], SZ_B);
735
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
341 #ifdef Z80_LOG_ADDRESS
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
342 log_address(&opts->gen, address, "Z80: %X @ %d\n");
539d12fa6a4d Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents: 734
diff changeset
343 #endif
626
7c46891a29b1 Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents: 625
diff changeset
344 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
345 switch(inst->op)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
346 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
347 case Z80_LD:
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
348 size = z80_size(inst);
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
349 switch (inst->addr_mode & 0x1F)
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
350 {
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
351 case Z80_REG:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
352 case Z80_REG_INDIRECT:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
353 if (size != SZ_B) {
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
354 num_cycles += 2;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
355 }
841
58606d16d35c Fix timing of certain variants of LD
Michael Pavone <pavone@retrodev.com>
parents: 840
diff changeset
356 if (inst->reg == Z80_I || inst->ea_reg == Z80_I || inst->reg == Z80_R || inst->ea_reg == Z80_R) {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
357 num_cycles += 1;
1767
8a29c250f352 More instruction timing fixes in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1761
diff changeset
358 } else if (inst->reg == Z80_USE_IMMED) {
8a29c250f352 More instruction timing fixes in old Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1761
diff changeset
359 num_cycles += 3;
506
a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 505
diff changeset
360 }
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
361 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
362 case Z80_IMMED:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
363 num_cycles += size == SZ_B ? 3 : 6;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
364 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
365 case Z80_IMMED_INDIRECT:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
366 num_cycles += 6;
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
367 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
368 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
369 case Z80_IY_DISPLACE:
1110
d1eed3b1121c Fix a couple of timing regressions in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1062
diff changeset
370 num_cycles += 8; //3 for displacement, 5 for address addition
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
371 break;
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
372 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
373 cycles(&opts->gen, num_cycles);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
374 if (inst->addr_mode & Z80_DIR) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
375 translate_z80_ea(inst, &dst_op, opts, DONT_READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
376 translate_z80_reg(inst, &src_op, opts);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
377 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
378 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
379 translate_z80_reg(inst, &dst_op, opts);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
380 }
1047
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
381 if (inst->reg == Z80_R) {
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
382 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
383 mov_rr(code, opts->regs[Z80_A], opts->regs[Z80_R], SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
384 and_ir(code, 0x80, opts->gen.scratch1, SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
385 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zr_off(Z80_R), SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
386 } else if (inst->ea_reg == Z80_R && inst->addr_mode == Z80_REG) {
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
387 mov_rr(code, opts->regs[Z80_R], opts->regs[Z80_A], SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
388 and_ir(code, 0x7F, opts->regs[Z80_A], SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
389 or_rdispr(code, opts->gen.context_reg, zr_off(Z80_R), opts->regs[Z80_A], SZ_B);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents: 1046
diff changeset
390 } else if (src_op.mode == MODE_REG_DIRECT) {
262
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
391 if(dst_op.mode == MODE_REG_DISPLACE8) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
392 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, size);
262
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
393 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
394 mov_rr(code, src_op.base, dst_op.base, size);
262
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
395 }
d97c9eca49f4 Implement ld to and from the I and R registers
Mike Pavone <pavone@retrodev.com>
parents: 261
diff changeset
396 } else if(src_op.mode == MODE_IMMED) {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
397 if(dst_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
398 mov_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
399 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
400 mov_ir(code, src_op.disp, dst_op.base, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
401 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
402 } else {
730
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
403 if(dst_op.mode == MODE_REG_DISPLACE8) {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
404 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
405 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
406 } else {
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
407 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, size);
38e9bee03749 More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 729
diff changeset
408 }
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
409 }
842
ba93a3941300 Set flags for ld a, r
Michael Pavone <pavone@retrodev.com>
parents: 841
diff changeset
410 if ((inst->ea_reg == Z80_I || inst->ea_reg == Z80_R) && inst->addr_mode == Z80_REG) {
ba93a3941300 Set flags for ld a, r
Michael Pavone <pavone@retrodev.com>
parents: 841
diff changeset
411 //ld a, i and ld a, r sets some flags
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
412 cmp_ir(code, 0, dst_op.base, SZ_B);
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
413 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
414 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
821
21a69dfb6ee7 Implement half carry for a couple of the trivial cases
Michael Pavone <pavone@retrodev.com>
parents: 819
diff changeset
415 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);;
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
416 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);;
659
759c38bf97f8 Minor Z80 core cleanup
Michael Pavone <pavone@retrodev.com>
parents: 657
diff changeset
417 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch1, SZ_B);
652
Michael Pavone <pavone@retrodev.com>
parents: 620 651
diff changeset
418 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
651
103d5cabbe14 Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents: 644
diff changeset
419 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
420 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
421 z80_save_ea(code, inst, opts);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
422 if (inst->addr_mode & Z80_DIR) {
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
423 z80_save_result(opts, inst);
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
424 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
425 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
426 case Z80_PUSH:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
427 cycles(&opts->gen, num_cycles + 1);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
428 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
429 if (inst->reg == Z80_AF) {
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
430 zreg_to_native(opts, Z80_A, opts->gen.scratch1);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
431 shl_ir(code, 8, opts->gen.scratch1, SZ_W);
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
432 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
433 and_ir(code, 0x28, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
434 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
435 ror_ir(code, 1, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
436 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_N), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
437 ror_ir(code, 1, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
438 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_PV), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
439 ror_ir(code, 2, opts->gen.scratch1, SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
440 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch1, SZ_B);
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
441 ror_ir(code, 2, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
442 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_Z), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
443 ror_ir(code, 1, opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
444 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_S), opts->gen.scratch1, SZ_B);
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
445 ror_ir(code, 1, opts->gen.scratch1, SZ_B);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
446 } else {
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
447 zreg_to_native(opts, inst->reg, opts->gen.scratch1);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
448 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
449 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
450 call(code, opts->write_16_highfirst);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
451 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
452 //the upper half of a register pair
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
453 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
454 case Z80_POP:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
455 cycles(&opts->gen, num_cycles);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
456 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
457 call(code, opts->read_16);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
458 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
459 if (inst->reg == Z80_AF) {
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
460
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
461 bt_ir(code, 0, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
462 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
463 bt_ir(code, 1, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
464 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
465 bt_ir(code, 2, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
466 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
467 bt_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
468 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
469 bt_ir(code, 6, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
470 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
471 bt_ir(code, 7, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
472 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_S));
1049
ef7ee9919a73 Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents: 1048
diff changeset
473 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
474 shr_ir(code, 8, opts->gen.scratch1, SZ_W);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
475 native_to_zreg(opts, opts->gen.scratch1, Z80_A);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
476 } else {
731
0835cd3dfc36 Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents: 730
diff changeset
477 native_to_zreg(opts, opts->gen.scratch1, inst->reg);
235
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
478 }
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
479 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents: 213
diff changeset
480 //the upper half of a register pair
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
481 break;
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
482 case Z80_EX:
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
483 cycles(&opts->gen, num_cycles);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
484 if (inst->addr_mode == Z80_REG) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
485 if(inst->reg == Z80_AF) {
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
486 zreg_to_native(opts, Z80_A, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
487 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_A), opts->gen.scratch2, SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
488 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_A), SZ_B);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
489 native_to_zreg(opts, opts->gen.scratch2, Z80_A);
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 467
diff changeset
490
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
491 //Flags are currently word aligned, so we can move
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
492 //them efficiently a word at a time
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
493 for (int f = ZF_C; f < ZF_NUM; f+=2) {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
494 mov_rdispr(code, opts->gen.context_reg, zf_off(f), opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
495 mov_rdispr(code, opts->gen.context_reg, zaf_off(f), opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
496 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zaf_off(f), SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
497 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(f), SZ_W);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
498 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
499 } else {
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
500 if (opts->regs[Z80_DE] >= 0 && opts->regs[Z80_HL] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
501 xchg_rr(code, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
502 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
503 zreg_to_native(opts, Z80_DE, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
504 zreg_to_native(opts, Z80_HL, opts->gen.scratch2);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
505 native_to_zreg(opts, opts->gen.scratch1, Z80_HL);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
506 native_to_zreg(opts, opts->gen.scratch2, Z80_DE);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
507 }
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
508 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
509 } else {
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
510 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
511 call(code, opts->read_8);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
512 if (opts->regs[inst->reg] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
513 xchg_rr(code, opts->regs[inst->reg], opts->gen.scratch1, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
514 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
515 zreg_to_native(opts, inst->reg, opts->gen.scratch2);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
516 xchg_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
517 native_to_zreg(opts, opts->gen.scratch2, inst->reg);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
518 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
519 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
520 call(code, opts->write_8);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
521 cycles(&opts->gen, 1);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
522 uint8_t high_reg = z80_high_reg(inst->reg);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
523 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
524 add_ir(code, 1, opts->gen.scratch1, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
525 call(code, opts->read_8);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
526 if (opts->regs[inst->reg] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
527 //even though some of the upper halves can be used directly
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
528 //the limitations on mixing *H regs with the REX prefix
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
529 //prevent us from taking advantage of it
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
530 uint8_t use_reg = opts->regs[inst->reg];
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
531 ror_ir(code, 8, use_reg, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
532 xchg_rr(code, use_reg, opts->gen.scratch1, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
533 //restore reg to normal rotation
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
534 ror_ir(code, 8, use_reg, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
535 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
536 zreg_to_native(opts, high_reg, opts->gen.scratch2);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
537 xchg_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
538 native_to_zreg(opts, opts->gen.scratch2, high_reg);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
539 }
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
540 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
541 add_ir(code, 1, opts->gen.scratch2, SZ_W);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
542 call(code, opts->write_8);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
543 cycles(&opts->gen, 2);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
544 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
545 break;
213
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
546 case Z80_EXX:
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
547 cycles(&opts->gen, num_cycles);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
548 zreg_to_native(opts, Z80_BC, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
549 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_BC), opts->gen.scratch2, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
550 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_BC), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
551 native_to_zreg(opts, opts->gen.scratch2, Z80_BC);
840
5822c6e5642f Fix timing of IM instruction
Michael Pavone <pavone@retrodev.com>
parents: 828
diff changeset
552
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
553 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
554 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_HL), opts->gen.scratch2, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
555 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_HL), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
556 native_to_zreg(opts, opts->gen.scratch2, Z80_HL);
840
5822c6e5642f Fix timing of IM instruction
Michael Pavone <pavone@retrodev.com>
parents: 828
diff changeset
557
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
558 zreg_to_native(opts, Z80_DE, opts->gen.scratch1);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
559 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_DE), opts->gen.scratch2, SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
560 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
561 native_to_zreg(opts, opts->gen.scratch2, Z80_DE);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 239
diff changeset
562 break;
272
9b04b57434b5 Implement LDI
Mike Pavone <pavone@retrodev.com>
parents: 269
diff changeset
563 case Z80_LDI: {
1044
1625555e346e Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1043
diff changeset
564 cycles(&opts->gen, num_cycles);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
565 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
566 call(code, opts->read_8);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
567 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
1052
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
568 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
593
5ef3fe516da9 Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents: 592
diff changeset
569 call(code, opts->write_8);
1052
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
570 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
571 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
572 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
573 and_ir(code, 0x8, opts->gen.scratch1, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
574 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
575 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
366c28ac6c55 Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents: 1051
diff changeset
576 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
591
966b46c68942 Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents: 590
diff changeset
577 cycles(&opts->gen, 2);
729
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
578 if (opts->regs[Z80_DE] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
579 add_ir(code, 1, opts->regs[Z80_DE], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
580 } else {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
581 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
582 }
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
583 if (opts->regs[Z80_HL] >= 0) {
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents: 716
diff changeset
584 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
9ef6db986982 Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken