Mercurial > repos > blastem

annotate analyze_olp.py @ 1971:80920c21bb52

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Add an event log soft flush and call it twice per frame in between hard flushes to netplay latency when there are insufficient hardware updates to flush packets in the middle of a frame
author Michael Pavone <pavone@retrodev.com>
date Fri, 08 May 2020 11:40:30 -0700
parents b1ad6339de4f
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
455
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1 #!/usr/bin/env python
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
3 from zipfile import ZipFile
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
4 from sys import exit, argv
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
5
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
6 def detect_rise(last, sample, bit):
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
7 mask = 1 << bit
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
8 return (not last & mask) and (sample & mask)
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
9
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
10 def detect_fall(last, sample, bit):
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
11 mask = 1 << bit
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
12 return (last & mask) and (not sample & mask)
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
13
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
14 def detect_high(sample, bit):
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
15 mask = 1 << bit
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
16 return sample & mask
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
17
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
18 def detect_low(sample, bit):
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
19 mask = 1 << bit
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
20 return not sample & mask
1146
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
21
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
22 def get_value(sample, bits):
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
23 value = 0
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
24 for i in xrange(0, len(bits)):
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
25 bit = bits[i]
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
26 value |= (sample >> bit & 1) << i
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
27 return value
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
28
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
29 def swizzle_mode4(row, col):
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
30 return (col & 1) | (row << 1) | (col << 8 & 0xFE00)
455
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
31
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
32 def analyze_delays(chanmap, datafile):
926
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
33 if 'M68K_CLK' in chanmap:
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
34 m68k_clk = chanmap['M68K CLK']
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
35 elif 'CLK' in chanmap:
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
36 m68k_clk = chanmap['CLK']
455
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
37 m_as = chanmap['!AS']
926
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
38 ram_oe = chanmap['RAM !LOE/!RFSH']
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
39 ram_ce = chanmap['RAM !CE']
455
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
40 last = False
926
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
41 prev = False
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
42 prevRefresh = False
455
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
43 clks = 0
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
44 as_start = 0
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
45 for line in datafile.readlines():
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
46 line = line.strip()
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
47 if line and not line.startswith(';'):
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
48 sample,_,num = line.partition('@')
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
49 sample = int(sample, 16)
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
50 if not (last is False):
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
51 if detect_rise(last, sample, m68k_clk):
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
52 clks = clks + 1
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
53 if detect_rise(last, sample, m_as):
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
54 as_clks = clks - as_start
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
55 if as_clks > 2:
926
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
56 if not (prev is False):
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
57 print '!AS held for', as_clks, 'cycles starting (delay of ' + str(as_clks - 2) + ') at', as_start, 'and ending at', clks, 'delta since last delay:', as_start - prev
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
58 else:
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
59 print '!AS held for', as_clks, 'cycles starting (delay of ' + str(as_clks - 2) + ') at', as_start, 'and ending at', clks
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
60 prev = as_start
455
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
61 elif detect_fall(last, sample, m_as):
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
62 as_start = clks
926
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
63 if detect_fall(last, sample, ram_oe) and detect_high( sample, ram_ce):
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
64 if prevRefresh is False:
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
65 print 'RAM refresh at ', clks
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
66 else:
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
67 print 'RAM refresh at', clks, 'delta since last:', clks-prevRefresh
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
68 prevRefresh = clks
455
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
69 last = sample
926
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
70
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
71 def analyze_refresh(chanmap, datafile):
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
72 if 'M68K_CLK' in chanmap:
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
73 m68k_clk = chanmap['M68K CLK']
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
74 elif 'CLK' in chanmap:
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
75 m68k_clk = chanmap['CLK']
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
76 ram_oe = chanmap['RAM !LOE/!RFSH']
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
77 ram_ce = chanmap['RAM !CE']
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
78 clks = 0
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
79 last = False
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
80 prevRefresh = False
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
81 for line in datafile.readlines():
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
82 line = line.strip()
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
83 if line and not line.startswith(';'):
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
84 sample,_,num = line.partition('@')
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
85 sample = int(sample, 16)
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
86 if not (last is False):
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
87 if detect_rise(last, sample, m68k_clk):
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
88 clks = clks + 1
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
89 if detect_fall(last, sample, ram_oe) and detect_high( sample, ram_ce):
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
90 if prevRefresh is False:
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
91 print 'RAM refresh at ', clks
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
92 else:
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
93 print 'RAM refresh at', clks, 'delta since last:', clks-prevRefresh
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
94 prevRefresh = clks
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
95 last = sample
1146
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
96
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
97
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
98 table_start = 0x3800
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
99 table_end = table_start + 0x600
1158
6854ab93d182 Adjust analyze_olp SAT address to match testpattern values rather than Space Hawks
Michael Pavone <pavone@retrodev.com>
parents: 1146
diff changeset
100 sat_start = 0x3E00 #0x3F00
1146
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
101 sat_xname = sat_start + 0x80
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
102 sat_end = sat_start + 0x100
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
103
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
104
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
105 def analyze_vram(chanmap, datafile):
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
106 address_bits = [chanmap['AD{0}'.format(i)] for i in xrange(0, 8)]
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
107 ras = chanmap['!RAS']
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
108 cas = chanmap['!CAS']
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
109 hsync = chanmap['!HSYNC']
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
110 state = 'begin'
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
111 last = False
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
112 for line in datafile.readlines():
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
113 line = line.strip()
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
114 if line and not line.startswith(';'):
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
115 sample,_,num = line.partition('@')
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
116 sample = int(sample, 16)
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
117 if not (last is False):
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
118 if detect_fall(last, sample, hsync):
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
119 print 'HSYNC low @ {0}'.format(num)
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
120 elif detect_rise(last, sample, hsync):
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
121 print 'HSYNC high @ {0}'.format(num)
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
122 if state == 'begin':
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
123 if detect_fall(last, sample, ras):
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
124 state = 'ras'
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
125 row = get_value(sample, address_bits)
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
126 elif detect_fall(last, sample, cas):
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
127 state = 'cas'
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
128 elif state == 'ras':
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
129 if detect_fall(last, sample, cas):
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
130 col = get_value(sample, address_bits)
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
131 address = swizzle_mode4(row, col)
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
132
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
133 if address < table_end and address >= table_start:
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
134 offset = (address - table_start)/2
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
135 desc = 'Map Row {0} Col {1}'.format(offset / 32, offset & 31)
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
136 elif address >= sat_start and address < sat_xname:
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
137 offset = address - sat_start
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
138 desc = 'Sprite {0} Y Read'.format(offset)
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
139 elif address >= sat_xname and address < sat_end:
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
140 offset = address - sat_xname
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
141 desc = 'Sprite {0} X/Name Read'.format(offset / 2)
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
142 else:
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
143 desc = 'Tile {0} Row {1}'.format(address / 32, ((address / 4) & 7) + (0.5 if address & 2 else 0))
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
144 print '{0:02X}:{1:02X} - {2:04X} @ {3} - {4}'.format(row, col, address, num, desc)
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
145 state = 'begin'
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
146 elif state == 'cas':
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
147 if detect_fall(last, sample, ras):
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
148 print 'refresh @ {0}'.format(num)
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
149 state = 'begin'
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
150 last = sample
1677
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
151
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
152 def analyze_z80_mreq(chanmap, datafile):
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
153 m1 = chanmap['!M1']
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
154 mreq = chanmap['!MREQ']
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
155 addressMask = 0x3FF
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
156 last = None
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
157 lastWasM1 = False
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
158 for line in datafile.readlines():
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
159 line = line.strip()
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
160 if line and not line.startswith(';'):
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
161 sample,_,num = line.partition('@')
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
162 sample = int(sample, 16)
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
163 if not (last is None):
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
164 if detect_rise(last, sample, mreq):
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
165 address = last & addressMask
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
166 if detect_low(last, m1):
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
167 print 'M1 read {0:02X} @ {1}'.format(address, num)
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
168 lastWasM1 = True
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
169 elif lastWasM1:
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
170 print 'Refresh {0:02X} @ {1}'.format(address, num)
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
171 lastWasM1 = False
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
172 else:
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
173 print 'Access {0:02X} @ {1}'.format(address, num)
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
174 last = sample
455
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
175
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
176 def main(args):
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
177 if len(args) < 2:
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
178 print 'Usage: analyze_olp.py filename'
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
179 exit(1)
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
180 olpfile = ZipFile(args[1], "r")
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
181 channelfile = olpfile.open('channel.labels')
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
182 channels = [line.strip() for line in channelfile.readlines()]
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
183 channelfile.close()
926
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
184 print channels
455
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
185 chanmap = {}
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
186 for i in xrange(0, len(channels)):
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
187 chanmap[channels[i]] = i
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
188 datafile = olpfile.open('data.ols')
1146
3e24de8d8073 Add support for SMS controllers
Michael Pavone <pavone@retrodev.com>
parents: 926
diff changeset
189 #analyze_delays(chanmap, datafile)
1677
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
190 #analyze_vram(chanmap, datafile)
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
191 #analyze_refresh(chanmap, datafile)
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
192 analyze_z80_mreq(chanmap, datafile)
926
b290343e5664 Added some stuff for detecting refresh delays in one of my old logic analyzer scripts. Needs cleanup
Michael Pavone <pavone@retrodev.com>
parents: 455
diff changeset
193 datafile.close()
1677
b1ad6339de4f Old changes to OLP analyzer script for analyzing Z80 memory requests
Michael Pavone <pavone@retrodev.com>
parents: 1158
diff changeset
194
455
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
195
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
196 if __name__ == '__main__':
be9c7b3e25ee Added analysis script used for investigating direct color DMA timing
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
197 main(argv)