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annotate fib.s68 @ 1971:80920c21bb52

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Add an event log soft flush and call it twice per frame in between hard flushes to netplay latency when there are insufficient hardware updates to flush packets in the middle of a frame
author Michael Pavone <pavone@retrodev.com>
date Fri, 08 May 2020 11:40:30 -0700
parents f7fe240a7da6
children b7ecd0d6a77b
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
19
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents: 1
diff changeset
1 dc.l $0, start
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents: 1
diff changeset
2 start:
1529
f7fe240a7da6 Updated fibonacci benchmark code to work with current test harness
Michael Pavone <pavone@retrodev.com>
parents: 20
diff changeset
3 moveq #42, d0
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
4 bsr fib
1529
f7fe240a7da6 Updated fibonacci benchmark code to work with current test harness
Michael Pavone <pavone@retrodev.com>
parents: 20
diff changeset
5 reset
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
6 fib:
1
5a2c1da6dd0f Make sure all operations are long-word length on fib example.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
7 cmp.l #2, d0
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
8 blt base
1
5a2c1da6dd0f Make sure all operations are long-word length on fib example.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
9 subq.l #1, d0
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
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10 move.l d0, -(a7)
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
11 bsr fib
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
12 move.l (a7), d1
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
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13 exg d0, d1
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
14 move.l d1, (a7)
1
5a2c1da6dd0f Make sure all operations are long-word length on fib example.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
15 subq.l #1, d0
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
16 bsr fib
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
17 move.l (a7)+, d1
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
18 add.l d1, d0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
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19 rts
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
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20 base:
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
21 moveq #1, d0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
22 rts