Mercurial > repos > blastem
annotate m68k.cpu @ 1971:80920c21bb52
Add an event log soft flush and call it twice per frame in between hard flushes to netplay latency when there are insufficient hardware updates to flush packets in the middle of a frame
author | Michael Pavone <pavone@retrodev.com> |
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date | Fri, 08 May 2020 11:40:30 -0700 |
parents | 9eec86183aae |
children | 7d4df6b74263 |
rev | line source |
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1 info |
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2 prefix m68k_ |
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3 opcode_size 16 |
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4 body m68k_run_op |
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5 header m68k.h |
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6 interrupt m68k_interrupt |
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7 include m68k_util.c |
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8 sync_cycle m68k_sync_cycle |
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9 |
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10 declare |
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11 typedef m68k_context *(*m68k_reset_handler)(m68k_context *context); |
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12 void init_m68k_opts(m68k_options *opts, memmap_chunk * memmap, uint32_t num_chunks, uint32_t clock_divider); |
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13 m68k_context *init_68k_context(m68k_options * opts, m68k_reset_handler reset_handler); |
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14 void m68k_reset(m68k_context *context); |
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15 void m68k_print_regs(m68k_context *context); |
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16 |
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17 regs |
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18 dregs 32 d0 d1 d2 d3 d4 d5 d6 d7 |
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19 aregs 32 a0 a1 a2 a3 a4 a5 a6 a7 |
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20 pc 32 |
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21 other_sp 32 |
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22 scratch1 32 |
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23 scratch2 32 |
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24 int_cycle 32 |
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25 prefetch 16 |
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26 int_priority 8 |
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27 int_num 8 |
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28 int_pending 8 |
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29 int_pending_num 8 |
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30 int_ack 8 |
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31 status 8 |
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32 ccr 8 |
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33 xflag 8 |
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34 nflag 8 |
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35 zflag 8 |
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36 vflag 8 |
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37 cflag 8 |
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38 reset_handler ptrvoid |
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39 mem_pointers ptrvoid 8 |
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40 |
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41 flags |
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42 register ccr |
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43 X 4 carry xflag |
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44 N 3 sign nflag |
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45 Z 2 zero zflag |
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46 V 1 overflow vflag |
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47 C 0 carry cflag |
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48 |
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49 m68k_prefetch |
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50 if dynarec |
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51 |
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52 ccall m68k_read16_noinc context pc |
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53 mov result prefetch |
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54 |
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55 end |
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56 |
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57 if interp |
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58 |
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59 mov pc scratch1 |
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60 ocall read_16 |
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61 mov scratch1 prefetch |
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62 |
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63 end |
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64 |
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65 add 2 pc pc |
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66 |
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67 check_user_mode_swap_ssp_usp |
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68 local tmp 8 |
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69 and 0x20 status tmp |
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70 if tmp |
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71 else |
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72 |
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73 xchg other_sp a7 |
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74 |
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75 end |
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76 |
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77 m68k_get_sr |
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78 lsl status 8 scratch1 |
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79 or ccr scratch1 scratch1 |
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80 |
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81 m68k_write32_lowfirst |
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82 arg value 32 |
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83 add 2 scratch2 scratch2 |
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84 mov value scratch1 |
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85 ocall write_16 |
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86 |
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87 sub 2 scratch2 scratch2 |
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88 lsr value 16 scratch1 |
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89 ocall write_16 |
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90 |
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91 m68k_write32 |
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92 arg value 32 |
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93 local tmp 32 |
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94 mov value tmp |
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95 lsr value 16 scratch1 |
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96 ocall write_16 |
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97 |
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98 add 2 scratch2 scratch2 |
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99 mov tmp scratch1 |
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100 ocall write_16 |
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101 |
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102 m68k_read32 |
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103 local tmp 32 |
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104 add 2 scratch1 tmp |
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105 ocall read_16 |
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106 xchg scratch1 tmp |
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107 ocall read_16 |
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108 lsl tmp 16 tmp |
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109 or tmp scratch1 scratch1 |
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110 |
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111 m68k_interrupt |
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112 cmp int_cycle cycles |
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113 if >=U |
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114 |
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115 #INT_PENDING_NONE |
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116 cmp 255 int_pending |
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117 if = |
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118 |
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119 mov int_priority int_pending |
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120 mov int_num int_pending_num |
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121 |
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122 else |
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123 |
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124 #INT_PENDING_SR_CHANGE |
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125 cmp 254 int_pending |
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126 if = |
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127 |
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128 mov int_priority int_pending |
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129 mov int_num int_pending_num |
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130 |
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131 else |
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132 |
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133 check_user_mode_swap_ssp_usp |
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134 |
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135 cycles 6 |
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136 #save status reg |
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137 sub 6 a7 a7 |
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138 m68k_get_sr |
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139 mov a7 scratch2 |
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140 ocall write_16 |
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141 |
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142 #update status register |
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143 and 0x78 status status |
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144 or int_priority status status |
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145 or 0x20 status status |
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146 |
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147 #Interrupt ack cycle |
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148 mov int_pending int_ack |
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149 if int_pending_num |
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150 cycles 4 |
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151 else |
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152 #TODO: do the whole E clock variable latency nonsense |
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153 cycles 13 |
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154 add 24 int_pending int_pending_num |
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155 end |
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156 |
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157 #save pc |
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158 add 2 a7 scratch2 |
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159 m68k_write32_lowfirst pc |
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160 |
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161 lsl int_pending_num 2 scratch1 |
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162 m68k_read32 |
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163 mov scratch1 pc |
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164 update_sync |
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165 end |
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166 |
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167 m68k_run_op |
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168 dispatch prefetch |
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169 |
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170 m68k_mem_src |
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171 arg address 32 |
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172 arg size 16 |
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173 arg isdst 8 |
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174 mov address scratch1 |
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175 if isdst |
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176 mov address scratch2 |
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177 meta ismem 1 |
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178 end |
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179 switch size |
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180 |
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181 case 0 |
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182 ocall read_8 |
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183 |
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184 case 1 |
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185 ocall read_16 |
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186 |
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187 case 2 |
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188 m68k_read32 |
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189 |
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190 end |
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191 meta op scratch1 |
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192 |
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193 m68k_write_size |
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194 arg size 16 |
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195 arg lowfirst 8 |
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196 switch size |
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197 case 0 |
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198 ocall write_8 |
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199 |
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200 case 1 |
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201 ocall write_16 |
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202 |
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203 case 2 |
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204 if lowfirst |
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205 m68k_write32_lowfirst scratch1 |
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206 else |
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207 m68k_write32 scratch1 |
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208 end |
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209 end |
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210 |
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211 m68k_index_word |
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212 m68k_prefetch |
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213 local disp 32 |
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214 and prefetch 255 disp |
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215 sext 16 disp disp |
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216 sext 32 disp disp |
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217 local index 16 |
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218 lsr prefetch 12 index |
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219 local isareg 16 |
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220 and index 8 isareg |
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221 and index 7 index |
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222 local islong 16 |
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|
223 and prefetch 2048 islong |
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224 |
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225 switch isareg |
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226 case 0 |
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227 switch islong |
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228 case 0 |
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229 sext 32 dregs.index scratch1 |
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|
230 case 2048 |
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231 mov dregs.index scratch1 |
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|
232 end |
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233 case 8 |
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234 switch islong |
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|
235 case 0 |
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|
236 sext 32 aregs.index scratch1 |
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|
237 case 2048 |
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238 mov aregs.index scratch1 |
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|
239 end |
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|
240 end |
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|
241 add disp scratch1 scratch1 |
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|
242 |
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243 m68k_fetch_op_ea |
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|
244 arg mode 16 |
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|
245 arg reg 16 |
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|
246 arg Z 16 |
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|
247 arg isdst 8 |
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|
248 switch mode |
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|
249 |
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|
250 case 0 |
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|
251 #data reg direct |
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|
252 meta op dregs.reg |
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|
253 if isdst |
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|
254 meta ismem 0 |
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|
255 end |
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|
256 |
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|
257 case 1 |
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|
258 #address reg direct |
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|
259 meta op aregs.reg |
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|
260 if isdst |
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|
261 meta ismem 0 |
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|
262 end |
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|
263 |
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diff
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|
264 case 2 |
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|
265 #address reg indirect |
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|
266 m68k_mem_src aregs.reg Z isdst |
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|
267 |
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|
268 case 3 |
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|
269 #postincrement |
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|
270 m68k_mem_src aregs.reg Z isdst |
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diff
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|
271 switch reg |
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|
272 case 7 |
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|
273 if Z |
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parents:
diff
changeset
|
274 addsize Z aregs.reg aregs.reg |
0c1491818f4b
WIP new 68K core using CPU DSL
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parents:
diff
changeset
|
275 else |
0c1491818f4b
WIP new 68K core using CPU DSL
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parents:
diff
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|
276 addsize 1 aregs.reg aregs.reg |
0c1491818f4b
WIP new 68K core using CPU DSL
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parents:
diff
changeset
|
277 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
278 default |
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WIP new 68K core using CPU DSL
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parents:
diff
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|
279 addsize Z aregs.reg aregs.reg |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
280 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
281 |
0c1491818f4b
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diff
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|
282 case 4 |
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parents:
diff
changeset
|
283 #predecrement |
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WIP new 68K core using CPU DSL
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parents:
diff
changeset
|
284 switch reg |
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WIP new 68K core using CPU DSL
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parents:
diff
changeset
|
285 case 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
286 if Z |
0c1491818f4b
WIP new 68K core using CPU DSL
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parents:
diff
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|
287 decsize Z aregs.reg aregs.reg |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
288 else |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
289 decsize 1 aregs.reg aregs.reg |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
290 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
291 default |
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WIP new 68K core using CPU DSL
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parents:
diff
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|
292 decsize Z aregs.reg aregs.reg |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
293 end |
0c1491818f4b
WIP new 68K core using CPU DSL
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parents:
diff
changeset
|
294 cycles 2 |
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WIP new 68K core using CPU DSL
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parents:
diff
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|
295 m68k_mem_src aregs.reg Z isdst |
0c1491818f4b
WIP new 68K core using CPU DSL
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parents:
diff
changeset
|
296 |
0c1491818f4b
WIP new 68K core using CPU DSL
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parents:
diff
changeset
|
297 case 5 |
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WIP new 68K core using CPU DSL
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parents:
diff
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|
298 #displacement |
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parents:
diff
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|
299 m68k_prefetch |
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parents:
diff
changeset
|
300 sext 32 prefetch scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
301 add scratch1 aregs.reg scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
302 m68k_mem_src scratch1 Z isdst |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
303 |
0c1491818f4b
WIP new 68K core using CPU DSL
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parents:
diff
changeset
|
304 case 6 |
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WIP new 68K core using CPU DSL
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parents:
diff
changeset
|
305 #indexed |
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parents:
diff
changeset
|
306 m68k_index_word |
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WIP new 68K core using CPU DSL
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parents:
diff
changeset
|
307 add aregs.reg scratch1 scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
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parents:
diff
changeset
|
308 |
0c1491818f4b
WIP new 68K core using CPU DSL
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parents:
diff
changeset
|
309 m68k_mem_src scratch1 Z isdst |
0c1491818f4b
WIP new 68K core using CPU DSL
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parents:
diff
changeset
|
310 case 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
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parents:
diff
changeset
|
311 #pc-relative and absolute modes |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
312 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
313 switch reg |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
314 case 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
315 #absolute short |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
316 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
317 sext 32 prefetch scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
318 m68k_mem_src scratch1 Z isdst |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
319 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
320 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
321 #absolute long |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
322 local address 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
323 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
324 lsl prefetch 16 address |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
325 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
326 or prefetch address scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
327 m68k_mem_src scratch1 Z isdst |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
328 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
329 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
330 #pc displaceent |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
331 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
332 sext 32 prefetch scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
333 add scratch1 pc scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
334 sub 2 scratch1 scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
335 m68k_mem_src scratch1 Z isdst |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
336 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
337 case 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
338 #pc indexed |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
339 m68k_index_word |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
340 add pc scratch1 scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
341 sub 2 scratch1 scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
342 m68k_mem_src scratch1 Z isdst |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
343 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
344 case 4 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
345 #immediate |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
346 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
347 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
348 local tmp32 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
349 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
350 lsl prefetch 16 tmp32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
351 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
352 or prefetch tmp32 scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
353 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
354 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
355 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
356 mov prefetch scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
357 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
358 meta op scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
359 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
360 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
361 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
362 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
363 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
364 m68k_fetch_src_ea |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
365 arg mode 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
366 arg reg 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
367 arg Z 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
368 m68k_fetch_op_ea mode reg Z 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
369 meta src op |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
370 switch mode |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
371 case 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
372 meta src_is_mem 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
373 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
374 meta src_is_mem 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
375 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
376 meta src_is_mem 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
377 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
378 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
379 m68k_fetch_dst_ea |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
380 arg mode 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
381 arg reg 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
382 arg Z 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
383 m68k_fetch_op_ea mode reg Z 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
384 meta dst op |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
385 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
386 m68k_save_dst |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
387 arg Z 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
388 if ismem |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
389 m68k_write_size Z 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
390 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
391 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
392 1101DDD0ZZMMMRRR add_ea_dn |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
393 invalid M 7 R 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
394 invalid M 7 R 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
395 invalid M 7 R 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
396 invalid Z 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
397 m68k_fetch_src_ea M R Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
398 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
399 add src dregs.D dregs.D Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
400 update_flags XNZVC |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
401 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
402 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
403 1101DDD1ZZMMMRRR add_dn_ea |
1941
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
404 invalid M 0 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
405 invalid M 1 |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
406 invalid M 7 R 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
407 invalid M 7 R 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
408 invalid M 7 R 4 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
409 invalid M 7 R 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
410 invalid M 7 R 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
411 invalid M 7 R 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
412 invalid Z 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
413 m68k_fetch_dst_ea M R Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
414 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
415 add dregs.D dst dst Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
416 update_flags XNZVC |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
417 m68k_save_dst Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
418 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
419 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
420 1101AAAZ11MMMRRR adda |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
421 invalid M 7 R 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
422 invalid M 7 R 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
423 invalid M 7 R 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
424 local size 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
425 local ext_src 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
426 if Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
427 mov 2 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
428 else |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
429 mov 1 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
430 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
431 m68k_fetch_src_ea M R size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
432 switch size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
433 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
434 sext 32 src ext_src |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
435 meta src ext_src |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
436 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
437 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
438 add src aregs.A aregs.A |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
439 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
440 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
441 00000110ZZMMMRRR addi |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
442 local immed 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
443 invalid Z 3 |
1941
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
444 invalid M 1 |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
445 invalid M 7 R 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
446 invalid M 7 R 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
447 invalid M 7 R 4 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
448 invalid M 7 R 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
449 invalid M 7 R 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
450 invalid M 7 R 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
451 #fetch immediate operand |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
452 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
453 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
454 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
455 lsl prefetch 16 immed |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
456 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
457 or prefetch immed immed |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
458 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
459 mov prefetch immed |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
460 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
461 #fetch dst EA |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
462 m68k_fetch_dst_ea M R Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
463 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
464 add immed dst dst Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
465 update_flags XNZVC |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
466 m68k_save_dst Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
467 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
468 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
469 0101III0ZZMMMRRR addq |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
470 invalid Z 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
471 invalid M 7 R 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
472 invalid M 7 R 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
473 invalid M 7 R 4 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
474 invalid M 7 R 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
475 invalid M 7 R 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
476 invalid M 7 R 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
477 local src 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
478 switch I |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
479 case 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
480 mov 8 src |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
481 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
482 mov I src |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
483 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
484 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
485 m68k_fetch_dst_ea M R Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
486 switch M |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
487 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
488 add src dst dst Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
489 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
490 add src dst dst Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
491 update_flags XNZVC |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
492 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
493 m68k_save_dst Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
494 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
495 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
496 1101DDD1ZZ000SSS addx_dy_dx |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
497 invalid Z 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
498 adc dregs.S dregs.D dregs.D Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
499 update_flags XNVC |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
500 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
501 case 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
502 local tmp8 8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
503 mov dregs.D tmp8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
504 if tmp8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
505 update_flags Z0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
506 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
507 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
508 local tmp16 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
509 mov dregs.D tmp16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
510 if tmp16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
511 update_flags Z0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
512 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
513 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
514 if dregs.D |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
515 update_flags Z0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
516 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
517 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
518 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
519 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
520 1101DDD1ZZ001SSS addx_ay_ax |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
521 invalid Z 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
522 if Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
523 decsize Z aregs.S aregs.S |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
524 else |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
525 switch S |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
526 case 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
527 sub 2 aregs.S aregs.S |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
528 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
529 decsize Z aregs.S aregs.S |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
530 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
531 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
532 mov aregs.S scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
533 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
534 case 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
535 ocall read_8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
536 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
537 ocall read_16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
538 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
539 m68k_read32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
540 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
541 mov scratch1 scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
542 if Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
543 decsize Z aregs.D aregs.D |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
544 else |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
545 switch D |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
546 case 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
547 sub 2 aregs.D aregs.D |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
548 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
549 decsize Z aregs.D aregs.D |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
550 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
551 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
552 mov aregs.D scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
553 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
554 case 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
555 ocall read_8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
556 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
557 ocall read_16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
558 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
559 m68k_read32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
560 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
561 adc scratch2 scratch1 scratch1 Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
562 update_flags XNVC |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
563 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
564 case 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
565 local tmp8 8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
566 mov dregs.D tmp8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
567 if tmp8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
568 update_flags Z0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
569 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
570 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
571 local tmp16 16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
572 mov dregs.D tmp16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
573 if tmp16 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
574 update_flags Z0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
575 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
576 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
577 if dregs.D |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
578 update_flags Z0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
579 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
580 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
581 mov aregs.D scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
582 m68k_write_size Z 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
583 m68k_prefetch |
1939
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
584 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
585 1100DDD0ZZMMMRRR and_ea_dn |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
586 invalid M 1 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
587 invalid M 7 R 5 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
588 invalid M 7 R 6 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
589 invalid M 7 R 7 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
590 invalid Z 3 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
591 m68k_fetch_src_ea M R Z |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
592 |
1939
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
593 and src dregs.D dregs.D Z |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
594 update_flags NZV0C0 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
595 m68k_prefetch |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
596 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
597 1100DDD1ZZMMMRRR and_dn_ea |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
598 invalid M 0 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
599 invalid M 1 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
600 invalid M 7 R 2 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
601 invalid M 7 R 3 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
602 invalid M 7 R 4 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
603 invalid M 7 R 5 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
604 invalid M 7 R 6 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
605 invalid M 7 R 7 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
606 invalid Z 3 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
607 m68k_fetch_dst_ea M R Z |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
608 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
609 and dregs.D dst dst Z |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
610 update_flags NZV0C0 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
611 m68k_save_dst Z |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
612 m68k_prefetch |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
613 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
614 00000010ZZMMMRRR andi |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
615 local immed 32 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
616 invalid Z 3 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
617 invalid M 1 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
618 invalid M 7 R 2 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
619 invalid M 7 R 3 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
620 invalid M 7 R 4 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
621 invalid M 7 R 5 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
622 invalid M 7 R 6 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
623 invalid M 7 R 7 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
624 #fetch immediate operand |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
625 m68k_prefetch |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
626 switch Z |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
627 case 2 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
628 lsl prefetch 16 immed |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
629 m68k_prefetch |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
630 or prefetch immed immed |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
631 default |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
632 mov prefetch immed |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
633 end |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
634 #fetch dst EA |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
635 m68k_fetch_dst_ea M R Z |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
636 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
637 and immed dst dst Z |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
638 update_flags NZV0C0 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
639 m68k_save_dst Z |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
640 m68k_prefetch |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
641 |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
642 0000001000111100 andi_to_ccr |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
643 #fetch immediate operand |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
644 m68k_prefetch |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
645 and prefetch ccr ccr |
84b32010ef8d
Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1838
diff
changeset
|
646 m68k_prefetch |
1940
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
647 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
648 1011DDD1ZZMMMRRR eor_dn_ea |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
649 invalid M 1 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
650 invalid M 7 R 2 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
651 invalid M 7 R 3 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
652 invalid M 7 R 4 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
653 invalid M 7 R 5 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
654 invalid M 7 R 6 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
655 invalid M 7 R 7 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
656 invalid Z 3 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
657 m68k_fetch_dst_ea M R Z |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
658 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
659 xor dregs.D dst dst Z |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
660 update_flags NZV0C0 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
661 m68k_save_dst Z |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
662 m68k_prefetch |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
663 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
664 00001010ZZMMMRRR eori |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
665 local immed 32 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
666 invalid Z 3 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
667 invalid M 1 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
668 invalid M 7 R 2 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
669 invalid M 7 R 3 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
670 invalid M 7 R 4 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
671 invalid M 7 R 5 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
672 invalid M 7 R 6 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
673 invalid M 7 R 7 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
674 #fetch immediate operand |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
675 m68k_prefetch |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
676 switch Z |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
677 case 2 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
678 lsl prefetch 16 immed |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
679 m68k_prefetch |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
680 or prefetch immed immed |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
681 default |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
682 mov prefetch immed |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
683 end |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
684 #fetch dst EA |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
685 m68k_fetch_dst_ea M R Z |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
686 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
687 xor immed dst dst Z |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
688 update_flags NZV0C0 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
689 m68k_save_dst Z |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
690 m68k_prefetch |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
691 |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
692 0000001000111100 eori_to_ccr |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
693 #fetch immediate operand |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
694 m68k_prefetch |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
695 xor prefetch ccr ccr |
048442b0cb62
Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents:
1939
diff
changeset
|
696 m68k_prefetch |
1941
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
697 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
698 1000DDD0ZZMMMRRR or_ea_dn |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
699 invalid M 1 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
700 invalid M 7 R 5 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
701 invalid M 7 R 6 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
702 invalid M 7 R 7 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
703 invalid Z 3 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
704 m68k_fetch_src_ea M R Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
705 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
706 or src dregs.D dregs.D Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
707 update_flags NZV0C0 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
708 m68k_prefetch |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
709 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
710 1000DDD1ZZMMMRRR or_dn_ea |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
711 invalid M 0 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
712 invalid M 1 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
713 invalid M 7 R 2 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
714 invalid M 7 R 3 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
715 invalid M 7 R 4 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
716 invalid M 7 R 5 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
717 invalid M 7 R 6 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
718 invalid M 7 R 7 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
719 invalid Z 3 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
720 m68k_fetch_dst_ea M R Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
721 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
722 or dregs.D dst dst Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
723 update_flags NZV0C0 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
724 m68k_save_dst Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
725 m68k_prefetch |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
726 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
727 00000000ZZMMMRRR ori |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
728 local immed 32 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
729 invalid Z 3 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
730 invalid M 1 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
731 invalid M 7 R 2 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
732 invalid M 7 R 3 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
733 invalid M 7 R 4 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
734 invalid M 7 R 5 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
735 invalid M 7 R 6 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
736 invalid M 7 R 7 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
737 #fetch immediate operand |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
738 m68k_prefetch |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
739 switch Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
740 case 2 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
741 lsl prefetch 16 immed |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
742 m68k_prefetch |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
743 or prefetch immed immed |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
744 default |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
745 mov prefetch immed |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
746 end |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
747 #fetch dst EA |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
748 m68k_fetch_dst_ea M R Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
749 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
750 or immed dst dst Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
751 update_flags NZV0C0 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
752 m68k_save_dst Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
753 m68k_prefetch |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
754 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
755 0000000000111100 ori_to_ccr |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
756 #fetch immediate operand |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
757 m68k_prefetch |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
758 or prefetch ccr ccr |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
759 m68k_prefetch |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
760 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
761 1001DDD0ZZMMMRRR sub_ea_dn |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
762 invalid M 7 R 5 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
763 invalid M 7 R 6 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
764 invalid M 7 R 7 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
765 invalid Z 3 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
766 m68k_fetch_src_ea M R Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
767 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
768 sub src dregs.D dregs.D Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
769 update_flags XNZVC |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
770 m68k_prefetch |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
771 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
772 1001DDD1ZZMMMRRR sub_dn_ea |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
773 invalid M 0 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
774 invalid M 1 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
775 invalid M 7 R 2 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
776 invalid M 7 R 3 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
777 invalid M 7 R 4 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
778 invalid M 7 R 5 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
779 invalid M 7 R 6 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
780 invalid M 7 R 7 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
781 invalid Z 3 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
782 m68k_fetch_dst_ea M R Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
783 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
784 sub dregs.D dst dst Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
785 update_flags XNZVC |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
786 m68k_save_dst Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
787 m68k_prefetch |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
788 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
789 1001AAAZ11MMMRRR suba |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
790 invalid M 7 R 5 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
791 invalid M 7 R 6 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
792 invalid M 7 R 7 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
793 local size 16 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
794 local ext_src 32 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
795 if Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
796 mov 2 size |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
797 else |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
798 mov 1 size |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
799 end |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
800 m68k_fetch_src_ea M R size |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
801 switch size |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
802 case 1 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
803 sext 32 src ext_src |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
804 meta src ext_src |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
805 end |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
806 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
807 sub src aregs.A aregs.A |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
808 m68k_prefetch |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
809 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
810 00000100ZZMMMRRR subi |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
811 local immed 32 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
812 invalid Z 3 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
813 invalid M 1 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
814 invalid M 7 R 2 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
815 invalid M 7 R 3 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
816 invalid M 7 R 4 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
817 invalid M 7 R 5 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
818 invalid M 7 R 6 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
819 invalid M 7 R 7 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
820 #fetch immediate operand |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
821 m68k_prefetch |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
822 switch Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
823 case 2 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
824 lsl prefetch 16 immed |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
825 m68k_prefetch |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
826 or prefetch immed immed |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
827 default |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
828 mov prefetch immed |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
829 end |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
830 #fetch dst EA |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
831 m68k_fetch_dst_ea M R Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
832 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
833 sub immed dst dst Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
834 update_flags XNZVC |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
835 m68k_save_dst Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
836 m68k_prefetch |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
837 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
838 0101III1ZZMMMRRR subq |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
839 invalid Z 3 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
840 invalid M 7 R 2 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
841 invalid M 7 R 3 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
842 invalid M 7 R 4 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
843 invalid M 7 R 5 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
844 invalid M 7 R 6 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
845 invalid M 7 R 7 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
846 local src 32 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
847 switch I |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
848 case 0 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
849 mov 8 src |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
850 default |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
851 mov I src |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
852 end |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
853 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
854 m68k_fetch_dst_ea M R Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
855 switch M |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
856 case 1 |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
857 sub src dst dst Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
858 default |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
859 sub src dst dst Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
860 update_flags XNZVC |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
861 end |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
862 m68k_save_dst Z |
9eec86183aae
Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents:
1940
diff
changeset
|
863 m68k_prefetch |
1838
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
864 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
865 00ZZRRRMMMEEESSS move |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
866 invalid Z 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
867 invalid M 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
868 invalid M 7 #not actually invalid, but will be handled separately due to DSL limitations |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
869 invalid E 7 S 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
870 invalid E 7 S 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
871 invalid E 7 S 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
872 local size 8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
873 local memsrc 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
874 #move uses a different size format than most instructions |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
876 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
877 mov 0 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
878 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
879 mov 2 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 case 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
881 mov 1 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
882 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
883 m68k_fetch_src_ea E S size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
884 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
885 if src_is_mem |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
886 #avoid clobbering src if we need scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 mov src memsrc |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
888 meta src memsrc |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
889 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
891 cmp 0 src size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
892 update_flags NZV0C0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
894 switch M |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
895 case 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
896 mov src dregs.R size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
899 mov aregs.R scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 mov src scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 m68k_write_size size 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
902 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
903 case 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
904 mov aregs.R scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
905 mov src scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 switch R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 case 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 if size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
909 addsize size aregs.R aregs.R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 else |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
911 addsize 1 aregs.R aregs.R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
912 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
913 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
914 addsize size aregs.R aregs.R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 m68k_write_size size 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
917 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
918 case 4 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
919 mov src scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
920 switch R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
921 case 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
922 if size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
923 decsize size aregs.R aregs.R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 else |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
925 decsize 1 aregs.R aregs.R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
926 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
927 default |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
928 decsize size aregs.R aregs.R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
929 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
930 mov aregs.R scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
931 m68k_write_size size 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
932 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
933 case 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
934 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
935 sext 32 prefetch scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
936 add aregs.R scratch2 scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
937 mov src scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
938 m68k_write_size size 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
939 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
940 case 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
941 m68k_index_word |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
942 add aregs.R scratch1 scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
943 mov src scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
944 m68k_write_size size 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
945 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
946 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
947 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
948 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
949 00ZZ00M111EEESSS move_abs |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
950 invalid E 7 S 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
951 invalid E 7 S 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
952 invalid E 7 S 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
953 invalid Z 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
954 local size 8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
955 local memsrc 32 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
956 #move uses a different size format than most instructions |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
957 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
958 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
959 mov 0 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
960 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
961 mov 2 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
962 case 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
963 mov 1 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
964 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
965 m68k_fetch_src_ea E S size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
966 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
967 if src_is_mem |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
968 #avoid clobbering src if we need scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
969 mov src memsrc |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
970 meta src memsrc |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
971 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
972 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
973 cmp 0 src size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
974 update_flags NZV0C0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
975 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
976 switch M |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
977 case 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
978 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
979 sext 32 prefetch scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
980 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
981 case 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
982 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
983 lsl prefetch 16 scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
984 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
985 or prefetch scratch2 scratch2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
986 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
987 mov src scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
988 m68k_write_size size 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
989 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
990 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
991 00ZZRRR001EEESSS movea |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
992 local size 8 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
993 invalid Z 0 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
994 invalid Z 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
995 invalid E 7 S 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
996 invalid E 7 S 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
997 invalid E 7 S 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
998 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
999 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1000 mov 2 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1001 case 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1002 mov 1 size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1003 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1004 m68k_fetch_src_ea E S size |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1005 switch Z |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1006 case 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1007 mov src aregs.R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1008 case 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1009 sext 32 src aregs.R |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1010 end |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1011 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1012 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1013 0100010011MMMRRR move_to_ccr |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1014 invalid M 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1015 invalid M 7 R 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1016 invalid M 7 R 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1017 invalid M 7 R 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1018 m68k_fetch_src_ea M R 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1019 mov scratch1 ccr |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1020 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1021 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1022 0100011011MMMRRR move_to_sr |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1023 invalid M 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1024 invalid M 7 R 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1025 invalid M 7 R 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1026 invalid M 7 R 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1027 m68k_fetch_src_ea M R 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1028 mov scratch1 ccr |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1029 lsr scratch1 8 status |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1030 update_sync |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1031 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1032 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1033 0100000011MMMRRR move_from_sr |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1034 invalid M 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1035 invalid M 7 R 2 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1036 invalid M 7 R 3 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1037 invalid M 7 R 4 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1038 invalid M 7 R 5 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1039 invalid M 7 R 6 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1040 invalid M 7 R 7 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1041 m68k_fetch_dst_ea M R 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1042 lsl status 8 scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1043 or ccr scratch1 scratch1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1044 mov scratch1 dst |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1045 m68k_save_dst 1 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1046 m68k_prefetch |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1047 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1048 0100111001110000 reset |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1049 cycles 124 |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1050 if reset_handler |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1051 pcall reset_handler m68k_reset_handler context |
0c1491818f4b
WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1052 end |