repos/blastem: 68kinst.h annotate

annotate 68kinst.h @ 1374:8f404b1fa572

Go back to resetting the refresh counter after a DMA. Probably not quite correct as it is probably reset on VDP triggered refresh, but this is close enough for now given the general limitations with my refresh code. VDP FIFO Testing seems to be passing 100% reliably again (was occassionally failing still with the last commit)

author	Michael Pavone <pavone@retrodev.com>
date	Tue, 23 May 2017 23:47:40 -0700
parents	faa3a4617f62
children	8554751f17b5

rev	line source
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	2 Copyright 2013 Michael Pavone
518 775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	3 This file is part of BlastEm.
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 226 diff changeset	5 */
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	6 #ifndef M68KINST_H_
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	7 #define M68KINST_H_
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	8
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	9 #include <stdint.h>
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	10
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	11 #ifdef M68030
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	12 #define M68020
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	13 #endif
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	14 #ifdef M68020
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	15 #define M68010
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	16 #endif
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	17
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	18 typedef enum {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 BIT_MOVEP_IMMED = 0,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	20 MOVE_BYTE,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	21 MOVE_LONG,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 MOVE_WORD,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	23 MISC,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	24 QUICK_ARITH_LOOP,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	25 BRANCH,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	26 MOVEQ,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	27 OR_DIV_SBCD,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	28 SUB_SUBX,
992 261995d06897 Implemented A line and F line traps. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	29 A_LINE,
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	30 CMP_XOR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	31 AND_MUL_ABCD_EXG,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	32 ADD_ADDX,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	33 SHIFT_ROTATE,
992 261995d06897 Implemented A line and F line traps. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	34 F_LINE
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	35 } m68k_optypes;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	36
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	37 typedef enum {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	38 M68K_ABCD,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	39 M68K_ADD,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	40 M68K_ADDX,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	41 M68K_AND,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	42 M68K_ANDI_CCR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	43 M68K_ANDI_SR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	44 M68K_ASL,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	45 M68K_ASR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	46 M68K_BCC,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	47 M68K_BCHG,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	48 M68K_BCLR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	49 M68K_BSET,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	50 M68K_BSR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	51 M68K_BTST,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	52 M68K_CHK,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	53 M68K_CLR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	54 M68K_CMP,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	55 M68K_DBCC,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	56 M68K_DIVS,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	57 M68K_DIVU,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	58 M68K_EOR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	59 M68K_EORI_CCR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	60 M68K_EORI_SR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	61 M68K_EXG,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	62 M68K_EXT,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	63 M68K_ILLEGAL,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	64 M68K_JMP,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	65 M68K_JSR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	66 M68K_LEA,
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	67 M68K_LINK,
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	68 M68K_LSL,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	69 M68K_LSR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	70 M68K_MOVE,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	71 M68K_MOVE_CCR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	72 M68K_MOVE_FROM_SR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	73 M68K_MOVE_SR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	74 M68K_MOVE_USP,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	75 M68K_MOVEM,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	76 M68K_MOVEP,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	77 M68K_MULS,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	78 M68K_MULU,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	79 M68K_NBCD,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	80 M68K_NEG,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	81 M68K_NEGX,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	82 M68K_NOP,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	83 M68K_NOT,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	84 M68K_OR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	85 M68K_ORI_CCR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	86 M68K_ORI_SR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	87 M68K_PEA,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	88 M68K_RESET,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	89 M68K_ROL,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	90 M68K_ROR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	91 M68K_ROXL,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	92 M68K_ROXR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	93 M68K_RTE,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	94 M68K_RTR,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	95 M68K_RTS,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	96 M68K_SBCD,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	97 M68K_SCC,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	98 M68K_STOP,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	99 M68K_SUB,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	100 M68K_SUBX,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	101 M68K_SWAP,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	102 M68K_TAS,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	103 M68K_TRAP,
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	104 M68K_TRAPV,
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	105 M68K_TST,
9 0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group Mike Pavone <pavone@retrodev.com> parents: 8 diff changeset	106 M68K_UNLK,
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	107 M68K_INVALID,
992 261995d06897 Implemented A line and F line traps. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	108 M68K_A_LINE_TRAP,
261995d06897 Implemented A line and F line traps. Michael Pavone <pavone@retrodev.com> parents: 981 diff changeset	109 M68K_F_LINE_TRAP,
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	110 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	111 M68K_BKPT,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	112 M68K_MOVE_FROM_CCR,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	113 M68K_MOVEC,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	114 M68K_MOVES,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	115 M68K_RTD,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	116 #endif
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	117 #ifdef M68020
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	118 M68K_BFCHG,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	119 M68K_BFCLR,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	120 M68K_BFEXTS,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	121 M68K_BFEXTU,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	122 M68K_BFFFO,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	123 M68K_BFINS,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	124 M68K_BFSET,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	125 M68K_BFTST,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	126 M68K_CALLM,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	127 M68K_CAS,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	128 M68K_CAS2,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	129 M68K_CHK2,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	130 M68K_CMP2,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	131 M68K_CP_BCC,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	132 M68K_CP_DBCC,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	133 M68K_CP_GEN,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	134 M68K_CP_RESTORE,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	135 M68K_CP_SAVE,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	136 M68K_CP_SCC,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	137 M68K_CP_TRAPCC,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	138 M68K_DIVSL,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	139 M68K_DIVUL,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	140 M68K_EXTB,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	141 M68K_PACK,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	142 M68K_RTM,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	143 M68K_TRAPCC,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	144 M68K_UNPK,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	145 #endif
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	146 } m68K_op;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	147
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	148 typedef enum {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	149 VAR_NORMAL,
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	150 VAR_QUICK,
8 23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	151 VAR_IMMEDIATE,
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	152 VAR_BYTE,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	153 VAR_WORD,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	154 VAR_LONG
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	155 } m68K_variant;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	156
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	157 typedef enum {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	158 OPSIZE_BYTE=0,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	159 OPSIZE_WORD,
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	160 OPSIZE_LONG,
10 4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	161 OPSIZE_INVALID,
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases Mike Pavone <pavone@retrodev.com> parents: 9 diff changeset	162 OPSIZE_UNSIZED
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	163 } m68K_opsizes;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	164
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	165 typedef enum {
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	166 //actual addressing mode field values
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	167 MODE_REG = 0,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	168 MODE_AREG,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	169 MODE_AREG_INDIRECT,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	170 MODE_AREG_POSTINC,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	171 MODE_AREG_PREDEC,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	172 MODE_AREG_DISPLACE,
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	173 MODE_AREG_INDEX_MEM, //bunch of relatively complicated modes
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	174 MODE_PC_INDIRECT_ABS_IMMED, //Modes that use the program counter, an absolute address or immediate value
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	175 //expanded values
79 d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	176 MODE_AREG_INDEX_DISP8,
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	177 #ifdef M68020
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	178 MODE_AREG_INDEX_BASE_DISP,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	179 MODE_AREG_PREINDEX,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	180 MODE_AREG_POSTINDEX,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	181 MODE_AREG_MEM_INDIRECT,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	182 MODE_AREG_BASE_DISP,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	183 MODE_INDEX_BASE_DISP,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	184 MODE_PREINDEX,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	185 MODE_POSTINDEX,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	186 MODE_MEM_INDIRECT,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	187 MODE_BASE_DISP,
79 d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	188 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	189 MODE_ABSOLUTE_SHORT,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	190 MODE_ABSOLUTE,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	191 MODE_PC_DISPLACE,
79 d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	192 MODE_PC_INDEX_DISP8,
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	193 #ifdef M68020
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	194 MODE_PC_INDEX_BASE_DISP,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	195 MODE_PC_PREINDEX,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	196 MODE_PC_POSTINDEX,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	197 MODE_PC_MEM_INDIRECT,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	198 MODE_PC_BASE_DISP,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	199 MODE_ZPC_INDEX_BASE_DISP,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	200 MODE_ZPC_PREINDEX,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	201 MODE_ZPC_POSTINDEX,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	202 MODE_ZPC_MEM_INDIRECT,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	203 MODE_ZPC_BASE_DISP,
79 d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	204 #endif
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	205 MODE_IMMEDIATE,
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	206 MODE_IMMEDIATE_WORD,//used to indicate an immediate operand that only uses a single extension word even for a long operation
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	207 MODE_UNUSED
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	208 } m68k_addr_modes;
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	209 #ifdef M68020
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	210 #define M68K_FLAG_BITFIELD 0x80
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	211 #endif
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	212
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	213 typedef enum {
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	214 COND_TRUE,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	215 COND_FALSE,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	216 COND_HIGH,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	217 COND_LOW_SAME,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	218 COND_CARRY_CLR,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	219 COND_CARRY_SET,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	220 COND_NOT_EQ,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	221 COND_EQ,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	222 COND_OVERF_CLR,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	223 COND_OVERF_SET,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	224 COND_PLUS,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	225 COND_MINUS,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	226 COND_GREATER_EQ,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	227 COND_LESS,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	228 COND_GREATER,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	229 COND_LESS_EQ
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	230 } m68K_condition;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	231
630 47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	232 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	233 typedef enum {
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	234 CR_SFC,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	235 CR_DFC,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	236 #ifdef M68020
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	237 CR_CACR,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	238 #endif
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	239 CR_USP,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	240 CR_VBR,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	241 #ifdef M68020
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	242 CR_CAAR,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	243 CR_MSP,
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	244 CR_ISP
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	245 #endif
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	246 } m68k_control_reg;
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	247
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	248 #ifdef M68020
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	249 #define MAX_HIGH_CR 0x804
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	250 #define MAX_LOW_CR 0x002
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	251 #else
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	252 #define MAX_HIGH_CR 0x801
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	253 #define MAX_LOW_CR 0x001
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	254 #endif
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	255
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	256 #endif
47123183c336 Improve support for disassembling 68010+ binaries Michael Pavone <pavone@retrodev.com> parents: 518 diff changeset	257
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	258 typedef struct {
636 22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	259 #ifdef M68020
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	260 uint16_t bitfield;
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	261 #endif
22e357678fad Add support for 68020 bitfield instructions Michael Pavone <pavone@retrodev.com> parents: 634 diff changeset	262 uint8_t addr_mode;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	263 union {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	264 struct {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	265 uint8_t pri;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	266 uint8_t sec;
637 d8d58eced22f Tiny bit of work towards supporting 68020 addressing modes in decoder/disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	267 #ifdef M68020
d8d58eced22f Tiny bit of work towards supporting 68020 addressing modes in decoder/disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	268 uint8_t scale;
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	269 uint8_t disp_sizes;
637 d8d58eced22f Tiny bit of work towards supporting 68020 addressing modes in decoder/disassembler Michael Pavone <pavone@retrodev.com> parents: 636 diff changeset	270 #endif
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	271 int32_t displacement;
638 8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	272 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	273 int32_t outer_disp;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler Michael Pavone <pavone@retrodev.com> parents: 637 diff changeset	274 #endif
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	275 } regs;
15 c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters. Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	276 uint32_t immed;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	277 } params;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	278 } m68k_op_info;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	279
208 3457dc6fd558 Tweaks to make blastem compatible with m68k-tester Mike Pavone <pavone@retrodev.com> parents: 134 diff changeset	280 typedef struct m68kinst {
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	281 uint8_t op;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	282 uint8_t variant;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	283 union {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	284 uint8_t size;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	285 uint8_t cond;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	286 } extra;
981 902c53d9c16f Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing Michael Pavone <pavone@retrodev.com> parents: 638 diff changeset	287 uint8_t bytes;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	288 uint32_t address;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	289 m68k_op_info src;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	290 m68k_op_info dst;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	291 } m68kinst;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	292
226 28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	293 typedef enum {
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	294 VECTOR_RESET_STACK,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	295 VECTOR_RESET_PC,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	296 VECTOR_ACCESS_FAULT,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	297 VECTOR_ADDRESS_ERROR,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	298 VECTOR_ILLEGAL_INST,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	299 VECTOR_INT_DIV_ZERO,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	300 VECTOR_CHK,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	301 VECTOR_TRAPV,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	302 VECTOR_PRIV_VIOLATION,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	303 VECTOR_TRACE,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	304 VECTOR_LINE_1010,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	305 VECTOR_LINE_1111,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	306 VECTOR_COPROC_VIOLATION=13,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	307 VECTOR_FORMAT_ERROR,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	308 VECTOR_UNINIT_INTERRUPT,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	309 VECTOR_SPURIOUS_INTERRUPT=24,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	310 VECTOR_INT_1,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	311 VECTOR_INT_2,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	312 VECTOR_INT_3,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	313 VECTOR_INT_4,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	314 VECTOR_INT_5,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	315 VECTOR_INT_6,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	316 VECTOR_INT_7,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	317 VECTOR_TRAP_0,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	318 VECTOR_TRAP_1,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	319 VECTOR_TRAP_2,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	320 VECTOR_TRAP_3,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	321 VECTOR_TRAP_4,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	322 VECTOR_TRAP_5,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	323 VECTOR_TRAP_6,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	324 VECTOR_TRAP_7,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	325 VECTOR_TRAP_8,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	326 VECTOR_TRAP_9,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	327 VECTOR_TRAP_10,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	328 VECTOR_TRAP_11,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	329 VECTOR_TRAP_12,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	330 VECTOR_TRAP_13,
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	331 VECTOR_TRAP_14,
1097 faa3a4617f62 Get Jaguar video interrupt working Michael Pavone <pavone@retrodev.com> parents: 992 diff changeset	332 VECTOR_TRAP_15,
faa3a4617f62 Get Jaguar video interrupt working Michael Pavone <pavone@retrodev.com> parents: 992 diff changeset	333 VECTOR_USER0 = 64
226 28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	334 } m68k_vector;
28a6697e847b Implement CHK instruction (not fully tested). Mike Pavone <pavone@retrodev.com> parents: 208 diff changeset	335
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	336 typedef int (format_label_fun)(char dst, uint32_t address, void * data);
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	337
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	338 uint16_t * m68k_decode(uint16_t * istream, m68kinst * dst, uint32_t address);
518 775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	339 uint32_t m68k_branch_target(m68kinst * inst, uint32_t dregs, uint32_t aregs);
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	340 uint8_t m68k_is_branch(m68kinst * inst);
775802dab98f Refactor debugger next command Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	341 uint8_t m68k_is_noncall_branch(m68kinst * inst);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 15 diff changeset	342 int m68k_disasm(m68kinst * decoded, char * dst);
634 4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	343 int m68k_disasm_labels(m68kinst * decoded, char * dst, format_label_fun label_fun, void * data);
4a6ec64acd79 Better support for labels sourced from VOS program module header Michael Pavone <pavone@retrodev.com> parents: 630 diff changeset	344 int m68k_default_label_fun(char * dst, uint32_t address, void * data);
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	345
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	346 #endif
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: 10 diff changeset	347

Mercurial > repos > blastem

annotate 68kinst.h @ 1374:8f404b1fa572