Mercurial > repos > blastem
annotate analyze_olp.py @ 1637:95880d947257
Fix for VRAM byte write order broke VDP FIFO testing ROM results. This change cleans up VRAM writes and fixes the regression while preserving the correct VRAM byte write order
author | Michael Pavone <pavone@retrodev.com> |
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date | Sun, 11 Nov 2018 22:39:29 -0800 |
parents | 6854ab93d182 |
children | b1ad6339de4f |
rev | line source |
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1 #!/usr/bin/env python |
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2 |
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3 from zipfile import ZipFile |
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4 from sys import exit, argv |
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5 |
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6 def detect_rise(last, sample, bit): |
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7 mask = 1 << bit |
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8 return (not last & mask) and (sample & mask) |
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9 |
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10 def detect_fall(last, sample, bit): |
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11 mask = 1 << bit |
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12 return (last & mask) and (not sample & mask) |
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13 |
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14 def detect_high(sample, bit): |
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15 mask = 1 << bit |
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16 return sample & mask |
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17 |
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18 def detect_low(sample, bit): |
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19 mask = 1 << bit |
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20 return not sample & mask |
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21 |
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22 def get_value(sample, bits): |
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23 value = 0 |
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24 for i in xrange(0, len(bits)): |
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25 bit = bits[i] |
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26 value |= (sample >> bit & 1) << i |
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27 return value |
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28 |
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29 def swizzle_mode4(row, col): |
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30 return (col & 1) | (row << 1) | (col << 8 & 0xFE00) |
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31 |
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32 def analyze_delays(chanmap, datafile): |
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33 if 'M68K_CLK' in chanmap: |
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34 m68k_clk = chanmap['M68K CLK'] |
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35 elif 'CLK' in chanmap: |
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36 m68k_clk = chanmap['CLK'] |
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37 m_as = chanmap['!AS'] |
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38 ram_oe = chanmap['RAM !LOE/!RFSH'] |
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39 ram_ce = chanmap['RAM !CE'] |
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40 last = False |
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41 prev = False |
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42 prevRefresh = False |
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43 clks = 0 |
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44 as_start = 0 |
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45 for line in datafile.readlines(): |
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46 line = line.strip() |
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47 if line and not line.startswith(';'): |
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48 sample,_,num = line.partition('@') |
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49 sample = int(sample, 16) |
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50 if not (last is False): |
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51 if detect_rise(last, sample, m68k_clk): |
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52 clks = clks + 1 |
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53 if detect_rise(last, sample, m_as): |
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54 as_clks = clks - as_start |
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55 if as_clks > 2: |
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56 if not (prev is False): |
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57 print '!AS held for', as_clks, 'cycles starting (delay of ' + str(as_clks - 2) + ') at', as_start, 'and ending at', clks, 'delta since last delay:', as_start - prev |
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58 else: |
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59 print '!AS held for', as_clks, 'cycles starting (delay of ' + str(as_clks - 2) + ') at', as_start, 'and ending at', clks |
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60 prev = as_start |
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61 elif detect_fall(last, sample, m_as): |
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62 as_start = clks |
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63 if detect_fall(last, sample, ram_oe) and detect_high( sample, ram_ce): |
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64 if prevRefresh is False: |
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65 print 'RAM refresh at ', clks |
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66 else: |
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67 print 'RAM refresh at', clks, 'delta since last:', clks-prevRefresh |
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68 prevRefresh = clks |
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69 last = sample |
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70 |
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71 def analyze_refresh(chanmap, datafile): |
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72 if 'M68K_CLK' in chanmap: |
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73 m68k_clk = chanmap['M68K CLK'] |
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74 elif 'CLK' in chanmap: |
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75 m68k_clk = chanmap['CLK'] |
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76 ram_oe = chanmap['RAM !LOE/!RFSH'] |
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77 ram_ce = chanmap['RAM !CE'] |
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78 clks = 0 |
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79 last = False |
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80 prevRefresh = False |
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81 for line in datafile.readlines(): |
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82 line = line.strip() |
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83 if line and not line.startswith(';'): |
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84 sample,_,num = line.partition('@') |
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85 sample = int(sample, 16) |
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86 if not (last is False): |
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87 if detect_rise(last, sample, m68k_clk): |
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88 clks = clks + 1 |
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89 if detect_fall(last, sample, ram_oe) and detect_high( sample, ram_ce): |
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90 if prevRefresh is False: |
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91 print 'RAM refresh at ', clks |
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92 else: |
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93 print 'RAM refresh at', clks, 'delta since last:', clks-prevRefresh |
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94 prevRefresh = clks |
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95 last = sample |
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96 |
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97 |
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98 table_start = 0x3800 |
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99 table_end = table_start + 0x600 |
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100 sat_start = 0x3E00 #0x3F00 |
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101 sat_xname = sat_start + 0x80 |
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102 sat_end = sat_start + 0x100 |
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103 |
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104 |
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105 def analyze_vram(chanmap, datafile): |
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106 address_bits = [chanmap['AD{0}'.format(i)] for i in xrange(0, 8)] |
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107 ras = chanmap['!RAS'] |
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108 cas = chanmap['!CAS'] |
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109 hsync = chanmap['!HSYNC'] |
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110 state = 'begin' |
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111 last = False |
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112 for line in datafile.readlines(): |
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113 line = line.strip() |
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114 if line and not line.startswith(';'): |
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115 sample,_,num = line.partition('@') |
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116 sample = int(sample, 16) |
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117 if not (last is False): |
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118 if detect_fall(last, sample, hsync): |
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119 print 'HSYNC low @ {0}'.format(num) |
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120 elif detect_rise(last, sample, hsync): |
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121 print 'HSYNC high @ {0}'.format(num) |
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122 if state == 'begin': |
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123 if detect_fall(last, sample, ras): |
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124 state = 'ras' |
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125 row = get_value(sample, address_bits) |
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126 elif detect_fall(last, sample, cas): |
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127 state = 'cas' |
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128 elif state == 'ras': |
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129 if detect_fall(last, sample, cas): |
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130 col = get_value(sample, address_bits) |
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131 address = swizzle_mode4(row, col) |
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132 |
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133 if address < table_end and address >= table_start: |
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134 offset = (address - table_start)/2 |
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135 desc = 'Map Row {0} Col {1}'.format(offset / 32, offset & 31) |
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136 elif address >= sat_start and address < sat_xname: |
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137 offset = address - sat_start |
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138 desc = 'Sprite {0} Y Read'.format(offset) |
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139 elif address >= sat_xname and address < sat_end: |
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140 offset = address - sat_xname |
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141 desc = 'Sprite {0} X/Name Read'.format(offset / 2) |
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142 else: |
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143 desc = 'Tile {0} Row {1}'.format(address / 32, ((address / 4) & 7) + (0.5 if address & 2 else 0)) |
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144 print '{0:02X}:{1:02X} - {2:04X} @ {3} - {4}'.format(row, col, address, num, desc) |
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145 state = 'begin' |
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146 elif state == 'cas': |
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147 if detect_fall(last, sample, ras): |
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148 print 'refresh @ {0}'.format(num) |
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149 state = 'begin' |
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150 last = sample |
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151 |
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152 def main(args): |
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153 if len(args) < 2: |
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154 print 'Usage: analyze_olp.py filename' |
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155 exit(1) |
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156 olpfile = ZipFile(args[1], "r") |
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157 channelfile = olpfile.open('channel.labels') |
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158 channels = [line.strip() for line in channelfile.readlines()] |
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159 channelfile.close() |
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160 print channels |
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161 chanmap = {} |
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162 for i in xrange(0, len(channels)): |
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163 chanmap[channels[i]] = i |
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164 datafile = olpfile.open('data.ols') |
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165 #analyze_delays(chanmap, datafile) |
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166 analyze_vram(chanmap, datafile) |
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167 datafile.close() |
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168 #datafile = olpfile.open('data.ols') |
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169 #analyze_refresh(chanmap, datafile) |
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170 |
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171 if __name__ == '__main__': |
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172 main(argv) |