repos/blastem: 68kinst.c annotate

annotate 68kinst.c @ 7:a74c2969e8f3

merge

author	Mike Pavone <pavone@retrodev.com>
date	Tue, 06 Nov 2012 02:07:45 -0800
parents	85699517043f
children	23b83d94c633

rev	line source
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1 #include "68kinst.h"
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2 #include <string.h>
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	3 #include <stdio.h>
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	4
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	5 uint32_t sign_extend16(uint32_t val)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	6 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	7 return (val & 0x8000) ? val \| 0xFFFF0000 : val;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	8 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	9
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	10 uint32_t sign_extend8(uint32_t val)
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	11 {
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	12 return (val & 0x80) ? val \| 0xFFFFFF00 : val;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	13 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	14
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	15 uint16_t m68k_decode_op_ex(uint16_t cur, uint8_t mode, uint8_t reg, uint8_t size, m68k_op_info *dst)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	16 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	17 uint16_t ext;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	18 dst->addr_mode = mode;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 switch(mode)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	20 {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	21 case MODE_REG:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 case MODE_AREG:
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	23 case MODE_AREG_INDIRECT:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	24 case MODE_AREG_POSTINC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	25 case MODE_AREG_PREDEC:
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	26 dst->params.regs.pri = reg;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	27 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	28 case MODE_AREG_DISPLACE:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	29 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	30 dst->params.regs.pri = reg;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	31 dst->params.regs.displacement = sign_extend16(ext);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	32 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	33 case MODE_AREG_INDEX_MEM:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	34 //TODO: implement me
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	35 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	36 case MODE_PC_INDIRECT_ABS_IMMED:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	37 switch(reg)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	38 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	39 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	40 dst->addr_mode = MODE_ABSOLUTE_SHORT;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	41 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	42 dst->params.u32 = sign_extend16(ext);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	43 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	44 case 1:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	45 dst->addr_mode = MODE_ABSOLUTE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	46 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	47 dst->params.u32 = ext << 16 \| *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	48 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	49 case 2:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	50 dst->addr_mode = MODE_PC_DISPLACE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	51 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	52 dst->params.regs.displacement = sign_extend16(ext);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	53 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	54 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	55 dst->addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	56 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	57 switch (size)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	58 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	59 case OPSIZE_BYTE:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	60 dst->params.u8 = ext;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	61 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	62 case OPSIZE_WORD:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	63 dst->params.u16 = ext;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	64 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	65 case OPSIZE_LONG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	66 dst->params.u32 = ext << 16 \| *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	67 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	68 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	69 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	70 //TODO: implement the rest of these
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	71 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	72 break;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	73 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	74 return cur;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	75 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	76
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	77 uint16_t m68k_decode_op(uint16_t cur, uint8_t size, m68k_op_info *dst)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	78 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	79 uint8_t mode = (*cur >> 3) & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	80 uint8_t reg = *cur & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	81 return m68k_decode_op_ex(cur, mode, reg, size, dst);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	82 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	83
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	84 void m68k_decode_cond(uint16_t op, m68kinst * decoded)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	85 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	86 decoded->extra.cond = (op >> 0x8) & 0xF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	87 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	88
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	89 uint8_t m68K_reg_quick_field(uint16_t op)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	90 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	91 return (op >> 9) & 0x7;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	92 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	93
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	94 uint16_t * m68K_decode(uint16_t * istream, m68kinst * decoded)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	95 {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	96 uint8_t optype = *istream >> 12;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	97 uint8_t size;
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	98 uint8_t reg;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	99 uint8_t opmode;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	100 uint32_t immed;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	101 decoded->op = M68K_INVALID;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	102 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_UNUSED;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	103 decoded->variant = VAR_NORMAL;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	104 switch(optype)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	105 {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	106 case BIT_MOVEP_IMMED:
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	107 if (*istream & 0x100) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	108 //BTST, BCHG, BCLR, BSET
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	109 switch ((*istream >> 6) & 0x3)
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	110 {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	111 case 0:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	112 decoded->op = M68K_BTST;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	113 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	114 case 1:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	115 decoded->op = M68K_BCHG;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	116 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	117 case 2:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	118 decoded->op = M68K_BCLR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	119 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	120 case 3:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	121 decoded->op = M68K_BSET;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	122 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	123 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	124 decoded->src.addr_mode = MODE_REG;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	125 decoded->src.params.regs.pri = m68K_reg_quick_field(*istream);
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	126 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->dst));
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	127 } else {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	128 switch ((*istream >> 9) & 0x7)
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	129 {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	130 case 0:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	131 if ((*istream & 0xFF) == 0x3C) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	132 decoded->op = M68K_ORI_CCR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	133 decoded->extra.size = OPSIZE_BYTE;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	134 decoded->src.addr_mode = MODE_IMMEDIATE;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	135 decoded->src.params.u8 = *(++istream);
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	136 } else if((*istream & 0xFF) == 0x7C) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	137 decoded->op = M68K_ORI_SR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	138 decoded->extra.size = OPSIZE_WORD;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	139 decoded->src.addr_mode = MODE_IMMEDIATE;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	140 decoded->src.params.u16 = *(++istream);
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	141 } else {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	142 //ORI, CMP2.b, CHK2.b
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	143 if ((*istream & 0xC0) != 0xC0) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	144 decoded->op = M68K_OR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	145 decoded->src.addr_mode = MODE_IMMEDIATE;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	146 decoded->extra.size = size = (*istream >> 6) & 3;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	147 reg = *istream & 0x7;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	148 opmode = (*istream >> 3) & 0x7;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	149 switch (size)
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	150 {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	151 case OPSIZE_BYTE:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	152 decoded->src.params.u8 = *(++istream);
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	153 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	154 case OPSIZE_WORD:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	155 decoded->src.params.16 = *(++istream);
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	156 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	157 case OPSIZE_LONG:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	158 immed = *(++istream);
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	159 decoded->src.params.u32 = immed << 16 \| *(++istream);
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	160 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	161 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	162 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	163 } else {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	164 #ifdef M68020
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	165 //TODO: Implement me for 68020 support
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	166 #endif
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	167 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	168 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	169 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	170 case 1:
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	171 //ANDI, ANDI to CCR, ANDI to SR, CMP2.w CHK2.w
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	172 if ((*istream & 0xFF) == 0x3C) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	173 decoded->op = M68K_ANDI_CCR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	174 decoded->extra.size = OPSIZE_BYTE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	175 decoded->src.addr_mode = MODE_IMMEDIATE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	176 decoded->src.params.u8 = *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	177 } else if((*istream & 0xFF) == 0x7C) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	178 decoded->op = M68K_ANDI_SR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	179 decoded->extra.size = OPSIZE_WORD;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	180 decoded->src.addr_mode = MODE_IMMEDIATE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	181 decoded->src.params.u16 = *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	182 } else {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	183 //ANDI, CMP2.w, CHK2.w
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	184 if ((*istream & 0xC0) != 0xC0) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	185 decoded->op = M68K_AND;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	186 decoded->src.addr_mode = MODE_IMMEDIATE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	187 decoded->extra.size = size = (*istream >> 6) & 3;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	188 reg = *istream & 0x7;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	189 opmode = (*istream >> 3) & 0x7;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	190 switch (size)
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	191 {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	192 case OPSIZE_BYTE:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	193 decoded->src.params.u8 = *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	194 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	195 case OPSIZE_WORD:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	196 decoded->src.params.16 = *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	197 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	198 case OPSIZE_LONG:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	199 immed = *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	200 decoded->src.params.u32 = immed << 16 \| *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	201 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	202 }
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	203 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	204 } else {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	205 #ifdef M68020
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	206 //TODO: Implement me for 68020 support
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	207 #endif
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	208 }
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	209 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	210 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	211 case 2:
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	212 //SUBI, CMP2.l, CHK2.l
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	213 if ((*istream & 0xC0) != 0xC0) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	214 decoded->op = M68K_SUB;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	215 decoded->src.addr_mode = MODE_IMMEDIATE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	216 decoded->extra.size = size = (*istream >> 6) & 3;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	217 reg = *istream & 0x7;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	218 opmode = (*istream >> 3) & 0x7;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	219 switch (size)
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	220 {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	221 case OPSIZE_BYTE:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	222 decoded->src.params.u8 = *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	223 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	224 case OPSIZE_WORD:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	225 decoded->src.params.16 = *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	226 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	227 case OPSIZE_LONG:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	228 immed = *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	229 decoded->src.params.u32 = immed << 16 \| *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	230 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	231 }
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	232 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	233 } else {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	234 #ifdef M68020
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	235 //TODO: Implement me for 68020 support
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	236 #endif
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	237 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	238 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	239 case 3:
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	240 //RTM, CALLM, ADDI
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	241 if ((*istream & 0xC0) != 0xC0) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	242 decoded->op = M68K_ADD;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	243 decoded->src.addr_mode = MODE_IMMEDIATE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	244 decoded->extra.size = size = (*istream >> 6) & 3;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	245 reg = *istream & 0x7;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	246 opmode = (*istream >> 3) & 0x7;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	247 switch (size)
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	248 {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	249 case OPSIZE_BYTE:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	250 decoded->src.params.u8 = *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	251 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	252 case OPSIZE_WORD:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	253 decoded->src.params.16 = *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	254 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	255 case OPSIZE_LONG:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	256 immed = *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	257 decoded->src.params.u32 = immed << 16 \| *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	258 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	259 }
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	260 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	261 } else {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	262 #ifdef M68020
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	263 //TODO: Implement me for 68020 support
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	264 #endif
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	265 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	266 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	267 case 4:
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	268 //BTST, BCHG, BCLR, BSET
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	269 switch ((*istream >> 6) & 0x3)
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	270 {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	271 case 0:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	272 decoded->op = M68K_BTST;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	273 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	274 case 1:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	275 decoded->op = M68K_BCHG;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	276 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	277 case 2:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	278 decoded->op = M68K_BCLR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	279 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	280 case 3:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	281 decoded->op = M68K_BSET;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	282 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	283 }
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	284 decoded->src.addr_mode = MODE_IMMEDIATE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	285 decoded->src.params.u8 = *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	286 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	287 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	288 case 5:
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	289 //EORI, EORI to CCR, EORI to SR
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	290 if ((*istream & 0xFF) == 0x3C) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	291 decoded->op = M68K_EORI_CCR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	292 decoded->extra.size = OPSIZE_BYTE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	293 decoded->src.addr_mode = MODE_IMMEDIATE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	294 decoded->src.params.u8 = *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	295 } else if((*istream & 0xFF) == 0x7C) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	296 decoded->op = M68K_EORI_SR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	297 decoded->extra.size = OPSIZE_WORD;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	298 decoded->src.addr_mode = MODE_IMMEDIATE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	299 decoded->src.params.u16 = *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	300 } else {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	301 //EORI, CMP2.w, CHK2.w
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	302 if ((*istream & 0xC0) != 0xC0) {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	303 decoded->op = M68K_EOR;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	304 decoded->src.addr_mode = MODE_IMMEDIATE;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	305 decoded->extra.size = size = (*istream >> 6) & 3;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	306 reg = *istream & 0x7;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	307 opmode = (*istream >> 3) & 0x7;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	308 switch (size)
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	309 {
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	310 case OPSIZE_BYTE:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	311 decoded->src.params.u8 = *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	312 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	313 case OPSIZE_WORD:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	314 decoded->src.params.16 = *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	315 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	316 case OPSIZE_LONG:
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	317 immed = *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	318 decoded->src.params.u32 = immed << 16 \| *(++istream);
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	319 break;
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	320 }
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	321 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	322 }
85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	323 }
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	324 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	325 case 6:
5 85699517043f More bit and immediate instructions Mike Pavone <pavone@retrodev.com> parents: 4 diff changeset	326
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	327 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	328 case 7:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	329 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	330 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	331 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	332 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	333 case MOVE_BYTE:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	334 case MOVE_LONG:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	335 case MOVE_WORD:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	336 decoded->op = M68K_MOVE;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	337 decoded->extra.size = optype == MOVE_BYTE ? OPSIZE_BYTE : (optype == MOVE_WORD ? OPSIZE_WORD : OPSIZE_LONG);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	338 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	339 istream = m68k_decode_op_ex(istream, (istream >> 6) & 0x7, m68K_reg_quick_field(istream), decoded->extra.size, &(decoded->dst));
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	340 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	341 case MISC:
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	342
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	343 if ((*istream & 0x1C0) == 0x1C0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	344 decoded->op = M68K_LEA;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	345 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	346 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	347 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	348 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	349 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	350 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	351 decoded->op = M68K_CHK;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	352 if ((*istream & 0x180) == 0x180) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	353 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	354 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	355 //only on M68020+
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	356 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	357 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	358 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	359 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	360 decoded->dst.addr_mode = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	361 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	362 optype = (*istream >> 9) & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	363 switch(optype)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	364 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	365 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	366 //Move from SR or NEGX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	367 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	368 case 1:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	369 //MOVE from CCR or CLR
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	370 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	371 case 2:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	372 //MOVE to CCR or NEG
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	373 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	374 case 3:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	375 //MOVE to SR or NOT
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	376 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	377 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	378 //EXT, EXTB, LINK.l, NBCD, SWAP, BKPT, PEA, MOVEM
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	379 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	380 case 5:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	381 //BGND, ILLEGAL, TAS, TST
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	382 optype = *istream & 0xFF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	383 if (optype == 0xFA) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	384 //BGND - CPU32 only
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	385 } else if (optype == 0xFC) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	386 decoded->op = M68K_ILLEGAL;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	387 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	388 size = (*istream & 0xC0) >> 6;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	389 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	390 decoded->op = M68K_TAS;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	391 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	392 decoded->op = M68K_TST;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	393 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	394 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	395 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	396 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	397 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	398 case 6:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	399 //MULU, MULS, DIVU, DIVUL, DIVS, DIVSL, MOVEM
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	400 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	401 case 7:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	402 //TRAP, LINK.w, UNLNK, MOVE USP, RESET, NOP, STOP, RTE, RTD, RTS, TRAPV, RTR, MOVEC, JSR, JMP
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	403 if (*istream & 0x80) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	404 //JSR, JMP
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	405 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	406 //it would appear bit 6 needs to be set for it to be a valid instruction here
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	407 switch((*istream >> 3) & 0x7)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	408 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	409 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	410 case 1:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	411 //TRAP
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	412 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	413 case 2:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	414 //LINK.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	415 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	416 case 3:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	417 //UNLNK
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	418 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	419 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	420 case 5:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	421 //MOVE USP
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	422 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	423 case 6:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	424 switch(*istream & 0x7)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	425 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	426 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	427 decoded->op = M68K_RESET;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	428 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	429 case 1:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	430 decoded->op = M68K_NOP;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	431 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	432 case 2:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	433 decoded->op = M68K_STOP;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	434 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	435 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	436 decoded->src.params.u16 =*(++istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	437 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	438 case 3:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	439 decoded->op = M68K_RTE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	440 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	441 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	442 #ifdef M68010
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	443 decoded->op = M68K_RTD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	444 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	445 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	446 decoded->src.params.u16 =*(++istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	447 #endif
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	448 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	449 case 5:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	450 decoded->op = M68K_RTS;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	451 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	452 case 6:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	453 decoded->op = M68K_TRAPV;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	454 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	455 case 7:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	456 decoded->op = M68K_RTR;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	457 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	458 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	459 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	460 case 7:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	461 //MOVEC
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	462 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	463 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	464 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	465 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	466 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	467 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	468 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	469 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	470 case QUICK_ARITH_LOOP:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	471 size = (*istream >> 6) & 3;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	472 if (size == 0x3) {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	473 //DBcc, TRAPcc or Scc
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	474 m68k_decode_cond(*istream, decoded);
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	475 switch ((*istream >> 3) & 0x7)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	476 {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	477 case 1: //DBcc
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	478 decoded->op = M68K_DBCC;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	479 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	480 decoded->src.params.u16 = *(++istream);
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	481 decoded->dst.addr_mode = MODE_REG;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	482 decoded->dst.params.regs.pri = *istream & 0x7;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	483 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	484 case 7: //TRAPcc
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	485 #ifdef M68020
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	486 decoded->op = M68K_TRAPCC;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	487 decoded->src.addr_mode = MODE_IMMEDIATE;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	488 //TODO: Figure out what to do with OPMODE and optional extention words
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	489 #endif
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	490 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	491 default: //Scc
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	492 decoded->op = M68K_SCC;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	493 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	494 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	495 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	496 } else {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	497 //ADDQ, SUBQ
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	498 decoded->variant = VAR_QUICK;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	499 decoded->extra.size = size;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	500 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	501 istream = m68k_decode_op(istream, size, &(decoded->dst));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	502 immed = m68K_reg_quick_field(*istream);
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	503 if (!immed) {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	504 immed = 8;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	505 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	506 switch (size)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	507 {
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	508 case OPSIZE_BYTE:
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	509 decoded->src.params.u8 = immed;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	510 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	511 case OPSIZE_WORD:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	512 decoded->src.params.u16 = immed;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	513 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	514 case OPSIZE_LONG:
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	515 decoded->src.params.u32 = immed;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	516 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	517 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	518 if (*istream & 0x100) {
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	519 decoded->op = M68K_SUB;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	520 } else {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	521 decoded->op = M68K_ADD;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	522 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	523 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	524 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	525 case BRANCH:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	526 m68k_decode_cond(*istream, decoded);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	527 decoded->op = decoded->extra.cond == COND_FALSE ? M68K_BSR : M68K_BCC;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	528 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	529 immed = *istream & 0xFF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	530 if (immed == 0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	531 decoded->variant = VAR_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	532 immed = *(++istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	533 immed = sign_extend16(immed);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	534 } else if (immed == 0xFF) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	535 decoded->variant = VAR_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	536 immed = *(++istream) << 16;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	537 immed \|= *(++istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	538 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	539 decoded->variant = VAR_BYTE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	540 immed = sign_extend8(immed);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	541 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	542 decoded->src.params.u32 = immed;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	543 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	544 case MOVEQ:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	545 decoded->op = M68K_MOVE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	546 decoded->variant = VAR_QUICK;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	547 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	548 decoded->src.params.u32 = sign_extend8(*istream & 0xFF);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	549 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	550 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	551 immed = *istream & 0xFF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	552 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	553 case OR_DIV_SBCD:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	554 //TODO: Implement me
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	555 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	556 case SUB_SUBX:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	557 size = *istream >> 6 & 0x3;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	558 decoded->op = M68K_SUB;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	559 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	560 //<ea> destination, SUBA.l or SUBX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	561 if (*istream & 0x6) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	562 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	563 //SUBA.l
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	564 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	565 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	566 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	567 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	568 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	569 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	570 istream = m68k_decode_op(istream, size, &(decoded->dst));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	571 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	572 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	573 //SUBX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	574 decoded->op = M68K_SUBX;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	575 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	576 istream = m68k_decode_op(istream, size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	577 decoded->dst.addr_mode = decoded->src.addr_mode;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	578 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	579 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	580 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	581 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	582 //SUBA.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	583 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	584 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	585 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	586 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	587 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	588 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	589 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	590 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	591 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	592 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	593 case RESERVED:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	594 //TODO: implement me
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	595 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	596 case CMP_XOR:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	597 size = *istream >> 6 & 0x3;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	598 decoded->op = M68K_CMP;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	599 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	600 //CMPM or EOR
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	601 istream = m68k_decode_op(istream, size, &(decoded->dst));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	602 if (decoded->src.addr_mode == MODE_AREG) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	603 //CMPM
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	604 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG_POSTINC;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	605 decoded->src.params.regs.pri = decoded->dst.params.regs.pri;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	606 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	607 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	608 //EOR
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	609 decoded->op = M68K_EOR;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	610 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	611 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	612 decoded->src.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	613 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	614 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	615 //CMP
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	616 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	617 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	618 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	619 istream = m68k_decode_op(istream, size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	620 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	621 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	622 case AND_MUL_ABCD_EXG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	623 //page 575 for summary
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	624 //EXG opmodes:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	625 //01000 -data regs
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	626 //01001 -addr regs
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	627 //10001 -one of each
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	628 //AND opmodes:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	629 //operand order bit + 2 size bits (00 - 10)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	630 //no address register direct addressing
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	631 //data register direct not allowed when <ea> is the source (operand order bit of 1)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	632 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	633 if ((*istream & 0xC0) == 0xC0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	634 decoded->op = M68K_MULS;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	635 decoded->extra.size = OPSIZE_WORD;
3 a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	636 decoded->dst.addr_mode = MODE_REG;
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	637 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	638 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	639 } else if(!(*istream & 0xF0)) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	640 decoded->op = M68K_ABCD;
3 a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	641 decoded->extra.size = OPSIZE_BYTE;
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	642 decoded->src.params.regs.pri = *istream & 0x7;
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	643 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	644 decoded->dst.addr_mode = decoded->src.addr_mode = (*istream & 8) ? MODE_AREG_PREDEC : MODE_REG;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	645 } else if(!(*istream & 0x30)) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	646 decoded->op = M68K_EXG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	647 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	648 decoded->src.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	649 decoded->dst.params.regs.pri = *istream & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	650 if (*istream & 0x8) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	651 if (*istream & 0x80) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	652 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	653 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	654 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	655 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	656 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	657 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	658 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	659 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	660 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	661 decoded->op = M68K_AND;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	662 decoded->extra.size = (*istream >> 6);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	663 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	664 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	665 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	666 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	667 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	668 if ((*istream & 0xC0) == 0xC0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	669 decoded->op = M68K_MULU;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	670 decoded->extra.size = OPSIZE_WORD;
3 a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	671 decoded->dst.addr_mode = MODE_REG;
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	672 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	673 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	674 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	675 decoded->op = M68K_AND;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	676 decoded->extra.size = (*istream >> 6);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	677 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	678 decoded->src.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	679 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	680 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	681 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	682 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	683 case ADD_ADDX:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	684 size = *istream >> 6 & 0x3;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	685 decoded->op = M68K_ADD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	686 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	687 //<ea> destination, ADDA.l or ADDX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	688 if (*istream & 0x6) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	689 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	690 //ADDA.l
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	691 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	692 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	693 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	694 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	695 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	696 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	697 istream = m68k_decode_op(istream, size, &(decoded->dst));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	698 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	699 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	700 //ADDX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	701 decoded->op = M68K_ADDX;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	702 //FIXME: Size is not technically correct
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	703 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	704 istream = m68k_decode_op(istream, size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	705 decoded->dst.addr_mode = decoded->src.addr_mode;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	706 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	707 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	708 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	709 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	710 //ADDA.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	711 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	712 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	713 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	714 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	715 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	716 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	717 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	718 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	719 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	720 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	721 case SHIFT_ROTATE:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	722 //TODO: Implement me
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	723 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	724 case COPROC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	725 //TODO: Implement me
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	726 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	727 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	728 return istream+1;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	729 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	730
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	731 char * mnemonics[] = {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	732 "abcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	733 "add",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	734 "addx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	735 "and",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	736 "andi_ccr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	737 "andi_sr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	738 "asl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	739 "asr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	740 "bcc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	741 "bchg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	742 "bclr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	743 "bset",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	744 "bsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	745 "btst",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	746 "chk",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	747 "clr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	748 "cmp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	749 "dbcc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	750 "divs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	751 "divu",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	752 "eor",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	753 "eori_ccr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	754 "eori_sr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	755 "exg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	756 "ext",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	757 "illegal",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	758 "jmp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	759 "jsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	760 "lea",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	761 "link",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	762 "lsl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	763 "lsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	764 "move",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	765 "move_ccr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	766 "move_from_sr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	767 "move_sr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	768 "move_usp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	769 "movem",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	770 "movep",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	771 "muls",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	772 "mulu",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	773 "nbcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	774 "neg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	775 "negx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	776 "nop",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	777 "not",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	778 "or",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	779 "ori_ccr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	780 "ori_sr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	781 "pea",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	782 "reset",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	783 "rol",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	784 "ror",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	785 "roxl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	786 "roxr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	787 "rte",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	788 "rtr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	789 "rts",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	790 "sbcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	791 "scc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	792 "stop",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	793 "sub",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	794 "subx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	795 "swap",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	796 "tas",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	797 "trap",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	798 "trapv",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	799 "tst",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	800 "unlnk",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	801 "invalid"
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	802 };
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	803
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	804 char * cond_mnem[] = {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	805 "ra",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	806 "f",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	807 "hi",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	808 "ls",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	809 "cc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	810 "cs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	811 "ne",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	812 "eq",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	813 "vc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	814 "vs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	815 "pl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	816 "mi",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	817 "ge",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	818 "lt",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	819 "gt",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	820 "le"
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	821 };
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	822
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	823 int m68K_disasm_op(m68k_op_info decoded, uint8_t size, char dst, int need_comma)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	824 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	825 char * c = need_comma ? "," : "";
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	826 switch(decoded->addr_mode)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	827 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	828 case MODE_REG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	829 return sprintf(dst, "%s d%d", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	830 case MODE_AREG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	831 return sprintf(dst, "%s a%d", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	832 case MODE_AREG_INDIRECT:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	833 return sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	834 case MODE_AREG_POSTINC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	835 return sprintf(dst, "%s (a%d)+", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	836 case MODE_AREG_PREDEC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	837 return sprintf(dst, "%s -(a%d)", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	838 case MODE_IMMEDIATE:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	839 return sprintf(dst, "%s #%d", c, size == OPSIZE_LONG ? decoded->params.u32 : (size == OPSIZE_WORD ? decoded->params.u16 : decoded->params.u8));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	840 default:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	841 return 0;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	842 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	843 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	844
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	845 int m68k_disasm(m68kinst * decoded, char * dst)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	846 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	847 int ret,op1len;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	848 uint8_t size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	849 if (decoded->op == M68K_BCC \|\| decoded->op == M68K_DBCC \|\| decoded->op == M68K_SCC) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	850 ret = strlen(mnemonics[decoded->op]) - 2;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	851 memcpy(dst, mnemonics[decoded->op], ret);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	852 dst[ret] = 0;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	853 strcat(dst, cond_mnem[decoded->extra.cond]);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	854 ret = strlen(dst);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	855 size = decoded->op = M68K_BCC ? OPSIZE_LONG : OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	856 } else if (decoded->op == M68K_BSR) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	857 size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	858 ret = sprintf(dst, "bsr%s", decoded->variant == VAR_BYTE ? ".s" : "");
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	859 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	860 size = decoded->extra.size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	861 ret = sprintf(dst, "%s%s.%c",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	862 mnemonics[decoded->op],
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	863 decoded->variant == VAR_QUICK ? "q" : "",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	864 decoded->extra.size == OPSIZE_BYTE ? 'b' : (size == OPSIZE_WORD ? 'w' : 'l'));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	865 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	866 op1len = m68K_disasm_op(&(decoded->src), size, dst + ret, 0);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	867 ret += op1len;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	868 ret += m68K_disasm_op(&(decoded->dst), size, dst + ret, op1len);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	869 return ret;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	870 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	871

Mercurial > repos > blastem

annotate 68kinst.c @ 7:a74c2969e8f3