Mercurial > repos > blastem
annotate fib.s68 @ 217:acd29e2664c6
Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
author | Mike Pavone <pavone@retrodev.com> |
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date | Sat, 20 Apr 2013 00:29:14 -0700 |
parents | f664eeb55cb4 |
children | 2455662378ed f7fe240a7da6 |
rev | line source |
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19
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
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1
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1 dc.l $0, start |
4717146a7606
Initial support for M68k reset vector, rather than starting at an arbitrary address
Mike Pavone <pavone@retrodev.com>
parents:
1
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2 start: |
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
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19
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3 moveq #36, d0 |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
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4 bsr fib |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
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5 illegal |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
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6 fib: |
1
5a2c1da6dd0f
Make sure all operations are long-word length on fib example.
Mike Pavone <pavone@retrodev.com>
parents:
0
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7 cmp.l #2, d0 |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
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8 blt base |
1
5a2c1da6dd0f
Make sure all operations are long-word length on fib example.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
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9 subq.l #1, d0 |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
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10 move.l d0, -(a7) |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
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11 bsr fib |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
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12 move.l (a7), d1 |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
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13 exg d0, d1 |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
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14 move.l d1, (a7) |
1
5a2c1da6dd0f
Make sure all operations are long-word length on fib example.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
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15 subq.l #1, d0 |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
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16 bsr fib |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
17 move.l (a7)+, d1 |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
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18 add.l d1, d0 |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
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19 rts |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
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20 base: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
21 moveq #1, d0 |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
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22 rts |