repos/blastem: 68kinst.c annotate

annotate 68kinst.c @ 6:b231162c8fdd

Add some logic analyzer captures, a Python script for analyzing said captures and a higher level analysis of the output

author	Mike Pavone <pavone@retrodev.com>
date	Tue, 06 Nov 2012 01:57:36 -0800
parents	6f6a2d7cc889
children	85699517043f

rev	line source
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	1 #include "68kinst.h"
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	2 #include <string.h>
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	3 #include <stdio.h>
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	4
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	5 uint32_t sign_extend16(uint32_t val)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	6 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	7 return (val & 0x8000) ? val \| 0xFFFF0000 : val;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	8 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	9
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	10 uint32_t sign_extend8(uint32_t val)
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	11 {
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	12 return (val & 0x80) ? val \| 0xFFFFFF00 : val;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	13 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	14
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	15 uint16_t m68k_decode_op_ex(uint16_t cur, uint8_t mode, uint8_t reg, uint8_t size, m68k_op_info *dst)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	16 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	17 uint16_t ext;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	18 dst->addr_mode = mode;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 switch(mode)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	20 {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	21 case MODE_REG:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 case MODE_AREG:
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	23 case MODE_AREG_INDIRECT:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	24 case MODE_AREG_POSTINC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	25 case MODE_AREG_PREDEC:
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	26 dst->params.regs.pri = reg;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	27 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	28 case MODE_AREG_DISPLACE:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	29 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	30 dst->params.regs.pri = reg;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	31 dst->params.regs.displacement = sign_extend16(ext);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	32 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	33 case MODE_AREG_INDEX_MEM:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	34 //TODO: implement me
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	35 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	36 case MODE_PC_INDIRECT_ABS_IMMED:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	37 switch(reg)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	38 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	39 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	40 dst->addr_mode = MODE_ABSOLUTE_SHORT;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	41 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	42 dst->params.u32 = sign_extend16(ext);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	43 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	44 case 1:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	45 dst->addr_mode = MODE_ABSOLUTE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	46 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	47 dst->params.u32 = ext << 16 \| *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	48 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	49 case 2:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	50 dst->addr_mode = MODE_PC_DISPLACE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	51 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	52 dst->params.regs.displacement = sign_extend16(ext);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	53 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	54 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	55 dst->addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	56 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	57 switch (size)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	58 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	59 case OPSIZE_BYTE:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	60 dst->params.u8 = ext;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	61 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	62 case OPSIZE_WORD:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	63 dst->params.u16 = ext;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	64 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	65 case OPSIZE_LONG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	66 dst->params.u32 = ext << 16 \| *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	67 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	68 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	69 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	70 //TODO: implement the rest of these
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	71 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	72 break;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	73 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	74 return cur;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	75 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	76
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	77 uint16_t m68k_decode_op(uint16_t cur, uint8_t size, m68k_op_info *dst)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	78 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	79 uint8_t mode = (*cur >> 3) & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	80 uint8_t reg = *cur & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	81 return m68k_decode_op_ex(cur, mode, reg, size, dst);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	82 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	83
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	84 void m68k_decode_cond(uint16_t op, m68kinst * decoded)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	85 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	86 decoded->extra.cond = (op >> 0x8) & 0xF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	87 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	88
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	89 uint8_t m68K_reg_quick_field(uint16_t op)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	90 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	91 return (op >> 9) & 0x7;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	92 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	93
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	94 uint16_t * m68K_decode(uint16_t * istream, m68kinst * decoded)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	95 {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	96 uint8_t optype = *istream >> 12;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	97 uint8_t size;
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	98 uint8_t reg;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	99 uint8_t opmode;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	100 uint32_t immed;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	101 decoded->op = M68K_INVALID;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	102 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_UNUSED;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	103 decoded->variant = VAR_NORMAL;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	104 switch(optype)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	105 {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	106 case BIT_MOVEP_IMMED:
4 6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	107 if (*istream & 0x100) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	108 //BTST, BCHG, BCLR, BSET
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	109 switch ((*istream >> 6) & 0x3)
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	110 {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	111 case 0:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	112 decoded->op = M68K_BTST;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	113 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	114 case 1:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	115 decoded->op = M68K_BCHG;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	116 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	117 case 2:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	118 decoded->op = M68K_BCLR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	119 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	120 case 3:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	121 decoded->op = M68K_BSET;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	122 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	123 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	124 decoded->src.addr_mode = MODE_REG;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	125 decoded->src.params.regs.pri = m68K_reg_quick_field(*istream);
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	126 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->dst));
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	127 } else {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	128 switch ((*istream >> 9) & 0x7)
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	129 {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	130 case 0:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	131 if ((*istream & 0xFF) == 0x3C) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	132 decoded->op = M68K_ORI_CCR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	133 decoded->extra.size = OPSIZE_BYTE;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	134 decoded->src.addr_mode = MODE_IMMEDIATE;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	135 decoded->src.params.u8 = *(++istream);
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	136 } else if((*istream & 0xFF) == 0x7C) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	137 decoded->op = M68K_ORI_SR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	138 decoded->extra.size = OPSIZE_WORD;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	139 decoded->src.addr_mode = MODE_IMMEDIATE;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	140 decoded->src.params.u16 = *(++istream);
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	141 } else {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	142 //ORI, CMP2.b, CHK2.b
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	143 if ((*istream & 0xC0) != 0xC0) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	144 decoded->op = M68K_OR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	145 decoded->src.addr_mode = MODE_IMMEDIATE;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	146 decoded->extra.size = size = (*istream >> 6) & 3;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	147 reg = *istream & 0x7;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	148 opmode = (*istream >> 3) & 0x7;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	149 switch (size)
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	150 {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	151 case OPSIZE_BYTE:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	152 decoded->src.params.u8 = *(++istream);
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	153 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	154 case OPSIZE_WORD:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	155 decoded->src.params.16 = *(++istream);
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	156 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	157 case OPSIZE_LONG:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	158 immed = *(++istream);
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	159 decoded->src.params.u32 = immed << 16 \| *(++istream);
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	160 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	161 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	162 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	163 } else {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	164 #ifdef M68020
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	165 //TODO: Implement me for 68020 support
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	166 #endif
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	167 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	168 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	169 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	170 case 1:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	171 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	172 case 2:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	173 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	174 case 3:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	175 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	176 case 4:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	177 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	178 case 5:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	179 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	180 case 6:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	181 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	182 case 7:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	183 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	184 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category" Mike Pavone <pavone@retrodev.com> parents: 3 diff changeset	185 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	186 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	187 case MOVE_BYTE:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	188 case MOVE_LONG:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	189 case MOVE_WORD:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	190 decoded->op = M68K_MOVE;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	191 decoded->extra.size = optype == MOVE_BYTE ? OPSIZE_BYTE : (optype == MOVE_WORD ? OPSIZE_WORD : OPSIZE_LONG);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	192 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	193 istream = m68k_decode_op_ex(istream, (istream >> 6) & 0x7, m68K_reg_quick_field(istream), decoded->extra.size, &(decoded->dst));
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	194 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	195 case MISC:
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	196
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	197 if ((*istream & 0x1C0) == 0x1C0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	198 decoded->op = M68K_LEA;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	199 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	200 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	201 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	202 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	203 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	204 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	205 decoded->op = M68K_CHK;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	206 if ((*istream & 0x180) == 0x180) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	207 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	208 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	209 //only on M68020+
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	210 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	211 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	212 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	213 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	214 decoded->dst.addr_mode = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	215 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	216 optype = (*istream >> 9) & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	217 switch(optype)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	218 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	219 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	220 //Move from SR or NEGX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	221 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	222 case 1:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	223 //MOVE from CCR or CLR
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	224 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	225 case 2:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	226 //MOVE to CCR or NEG
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	227 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	228 case 3:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	229 //MOVE to SR or NOT
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	230 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	231 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	232 //EXT, EXTB, LINK.l, NBCD, SWAP, BKPT, PEA, MOVEM
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	233 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	234 case 5:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	235 //BGND, ILLEGAL, TAS, TST
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	236 optype = *istream & 0xFF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	237 if (optype == 0xFA) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	238 //BGND - CPU32 only
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	239 } else if (optype == 0xFC) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	240 decoded->op = M68K_ILLEGAL;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	241 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	242 size = (*istream & 0xC0) >> 6;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	243 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	244 decoded->op = M68K_TAS;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	245 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	246 decoded->op = M68K_TST;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	247 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	248 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	249 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	250 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	251 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	252 case 6:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	253 //MULU, MULS, DIVU, DIVUL, DIVS, DIVSL, MOVEM
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	254 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	255 case 7:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	256 //TRAP, LINK.w, UNLNK, MOVE USP, RESET, NOP, STOP, RTE, RTD, RTS, TRAPV, RTR, MOVEC, JSR, JMP
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	257 if (*istream & 0x80) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	258 //JSR, JMP
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	259 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	260 //it would appear bit 6 needs to be set for it to be a valid instruction here
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	261 switch((*istream >> 3) & 0x7)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	262 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	263 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	264 case 1:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	265 //TRAP
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	266 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	267 case 2:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	268 //LINK.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	269 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	270 case 3:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	271 //UNLNK
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	272 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	273 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	274 case 5:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	275 //MOVE USP
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	276 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	277 case 6:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	278 switch(*istream & 0x7)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	279 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	280 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	281 decoded->op = M68K_RESET;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	282 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	283 case 1:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	284 decoded->op = M68K_NOP;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	285 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	286 case 2:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	287 decoded->op = M68K_STOP;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	288 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	289 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	290 decoded->src.params.u16 =*(++istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	291 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	292 case 3:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	293 decoded->op = M68K_RTE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	294 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	295 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	296 #ifdef M68010
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	297 decoded->op = M68K_RTD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	298 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	299 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	300 decoded->src.params.u16 =*(++istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	301 #endif
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	302 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	303 case 5:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	304 decoded->op = M68K_RTS;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	305 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	306 case 6:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	307 decoded->op = M68K_TRAPV;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	308 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	309 case 7:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	310 decoded->op = M68K_RTR;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	311 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	312 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	313 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	314 case 7:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	315 //MOVEC
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	316 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	317 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	318 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	319 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	320 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	321 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	322 }
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	323 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	324 case QUICK_ARITH_LOOP:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	325 size = (*istream >> 6) & 3;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	326 if (size == 0x3) {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	327 //DBcc, TRAPcc or Scc
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	328 m68k_decode_cond(*istream, decoded);
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	329 switch ((*istream >> 3) & 0x7)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	330 {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	331 case 1: //DBcc
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	332 decoded->op = M68K_DBCC;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	333 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	334 decoded->src.params.u16 = *(++istream);
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	335 decoded->dst.addr_mode = MODE_REG;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	336 decoded->dst.params.regs.pri = *istream & 0x7;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	337 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	338 case 7: //TRAPcc
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	339 #ifdef M68020
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	340 decoded->op = M68K_TRAPCC;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	341 decoded->src.addr_mode = MODE_IMMEDIATE;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	342 //TODO: Figure out what to do with OPMODE and optional extention words
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	343 #endif
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	344 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	345 default: //Scc
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	346 decoded->op = M68K_SCC;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	347 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	348 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	349 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	350 } else {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	351 //ADDQ, SUBQ
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	352 decoded->variant = VAR_QUICK;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	353 decoded->extra.size = size;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	354 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	355 istream = m68k_decode_op(istream, size, &(decoded->dst));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	356 immed = m68K_reg_quick_field(*istream);
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	357 if (!immed) {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	358 immed = 8;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	359 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	360 switch (size)
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	361 {
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	362 case OPSIZE_BYTE:
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	363 decoded->src.params.u8 = immed;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	364 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	365 case OPSIZE_WORD:
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	366 decoded->src.params.u16 = immed;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	367 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	368 case OPSIZE_LONG:
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	369 decoded->src.params.u32 = immed;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	370 break;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	371 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	372 if (*istream & 0x100) {
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	373 decoded->op = M68K_SUB;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	374 } else {
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	375 decoded->op = M68K_ADD;
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	376 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	377 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	378 break;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	379 case BRANCH:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	380 m68k_decode_cond(*istream, decoded);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	381 decoded->op = decoded->extra.cond == COND_FALSE ? M68K_BSR : M68K_BCC;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	382 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	383 immed = *istream & 0xFF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	384 if (immed == 0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	385 decoded->variant = VAR_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	386 immed = *(++istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	387 immed = sign_extend16(immed);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	388 } else if (immed == 0xFF) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	389 decoded->variant = VAR_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	390 immed = *(++istream) << 16;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	391 immed \|= *(++istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	392 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	393 decoded->variant = VAR_BYTE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	394 immed = sign_extend8(immed);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	395 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	396 decoded->src.params.u32 = immed;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	397 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	398 case MOVEQ:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	399 decoded->op = M68K_MOVE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	400 decoded->variant = VAR_QUICK;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	401 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	402 decoded->src.params.u32 = sign_extend8(*istream & 0xFF);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	403 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	404 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	405 immed = *istream & 0xFF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	406 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	407 case OR_DIV_SBCD:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	408 //TODO: Implement me
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	409 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	410 case SUB_SUBX:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	411 size = *istream >> 6 & 0x3;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	412 decoded->op = M68K_SUB;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	413 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	414 //<ea> destination, SUBA.l or SUBX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	415 if (*istream & 0x6) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	416 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	417 //SUBA.l
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	418 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	419 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	420 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	421 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	422 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	423 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	424 istream = m68k_decode_op(istream, size, &(decoded->dst));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	425 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	426 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	427 //SUBX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	428 decoded->op = M68K_SUBX;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	429 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	430 istream = m68k_decode_op(istream, size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	431 decoded->dst.addr_mode = decoded->src.addr_mode;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	432 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	433 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	434 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	435 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	436 //SUBA.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	437 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	438 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	439 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	440 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	441 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	442 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	443 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	444 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	445 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	446 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	447 case RESERVED:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	448 //TODO: implement me
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	449 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	450 case CMP_XOR:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	451 size = *istream >> 6 & 0x3;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	452 decoded->op = M68K_CMP;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	453 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	454 //CMPM or EOR
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	455 istream = m68k_decode_op(istream, size, &(decoded->dst));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	456 if (decoded->src.addr_mode == MODE_AREG) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	457 //CMPM
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	458 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG_POSTINC;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	459 decoded->src.params.regs.pri = decoded->dst.params.regs.pri;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	460 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	461 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	462 //EOR
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	463 decoded->op = M68K_EOR;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	464 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	465 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	466 decoded->src.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	467 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	468 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	469 //CMP
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	470 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	471 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	472 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	473 istream = m68k_decode_op(istream, size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	474 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	475 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	476 case AND_MUL_ABCD_EXG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	477 //page 575 for summary
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	478 //EXG opmodes:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	479 //01000 -data regs
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	480 //01001 -addr regs
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	481 //10001 -one of each
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	482 //AND opmodes:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	483 //operand order bit + 2 size bits (00 - 10)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	484 //no address register direct addressing
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	485 //data register direct not allowed when <ea> is the source (operand order bit of 1)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	486 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	487 if ((*istream & 0xC0) == 0xC0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	488 decoded->op = M68K_MULS;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	489 decoded->extra.size = OPSIZE_WORD;
3 a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	490 decoded->dst.addr_mode = MODE_REG;
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	491 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	492 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	493 } else if(!(*istream & 0xF0)) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	494 decoded->op = M68K_ABCD;
3 a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	495 decoded->extra.size = OPSIZE_BYTE;
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	496 decoded->src.params.regs.pri = *istream & 0x7;
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	497 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	498 decoded->dst.addr_mode = decoded->src.addr_mode = (*istream & 8) ? MODE_AREG_PREDEC : MODE_REG;
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	499 } else if(!(*istream & 0x30)) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	500 decoded->op = M68K_EXG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	501 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	502 decoded->src.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	503 decoded->dst.params.regs.pri = *istream & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	504 if (*istream & 0x8) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	505 if (*istream & 0x80) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	506 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	507 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	508 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	509 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	510 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	511 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	512 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	513 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	514 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	515 decoded->op = M68K_AND;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	516 decoded->extra.size = (*istream >> 6);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	517 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	518 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	519 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	520 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	521 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	522 if ((*istream & 0xC0) == 0xC0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	523 decoded->op = M68K_MULU;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	524 decoded->extra.size = OPSIZE_WORD;
3 a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	525 decoded->dst.addr_mode = MODE_REG;
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding Mike Pavone <pavone@retrodev.com> parents: 2 diff changeset	526 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	527 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	528 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	529 decoded->op = M68K_AND;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	530 decoded->extra.size = (*istream >> 6);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	531 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	532 decoded->src.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	533 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	534 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	535 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	536 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	537 case ADD_ADDX:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	538 size = *istream >> 6 & 0x3;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	539 decoded->op = M68K_ADD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	540 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	541 //<ea> destination, ADDA.l or ADDX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	542 if (*istream & 0x6) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	543 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	544 //ADDA.l
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	545 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	546 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	547 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	548 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	549 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	550 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	551 istream = m68k_decode_op(istream, size, &(decoded->dst));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	552 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	553 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	554 //ADDX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	555 decoded->op = M68K_ADDX;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	556 //FIXME: Size is not technically correct
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	557 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	558 istream = m68k_decode_op(istream, size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	559 decoded->dst.addr_mode = decoded->src.addr_mode;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	560 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	561 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	562 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	563 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	564 //ADDA.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	565 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	566 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	567 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	568 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	569 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	570 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	571 decoded->dst.params.regs.pri = m68K_reg_quick_field(*istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	572 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	573 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	574 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	575 case SHIFT_ROTATE:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	576 //TODO: Implement me
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	577 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	578 case COPROC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	579 //TODO: Implement me
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	580 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	581 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	582 return istream+1;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	583 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	584
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	585 char * mnemonics[] = {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	586 "abcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	587 "add",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	588 "addx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	589 "and",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	590 "andi_ccr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	591 "andi_sr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	592 "asl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	593 "asr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	594 "bcc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	595 "bchg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	596 "bclr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	597 "bset",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	598 "bsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	599 "btst",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	600 "chk",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	601 "clr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	602 "cmp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	603 "dbcc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	604 "divs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	605 "divu",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	606 "eor",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	607 "eori_ccr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	608 "eori_sr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	609 "exg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	610 "ext",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	611 "illegal",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	612 "jmp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	613 "jsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	614 "lea",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	615 "link",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	616 "lsl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	617 "lsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	618 "move",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	619 "move_ccr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	620 "move_from_sr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	621 "move_sr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	622 "move_usp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	623 "movem",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	624 "movep",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	625 "muls",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	626 "mulu",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	627 "nbcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	628 "neg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	629 "negx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	630 "nop",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	631 "not",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	632 "or",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	633 "ori_ccr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	634 "ori_sr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	635 "pea",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	636 "reset",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	637 "rol",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	638 "ror",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	639 "roxl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	640 "roxr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	641 "rte",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	642 "rtr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	643 "rts",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	644 "sbcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	645 "scc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	646 "stop",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	647 "sub",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	648 "subx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	649 "swap",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	650 "tas",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	651 "trap",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	652 "trapv",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	653 "tst",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	654 "unlnk",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	655 "invalid"
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	656 };
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	657
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	658 char * cond_mnem[] = {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	659 "ra",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	660 "f",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	661 "hi",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	662 "ls",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	663 "cc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	664 "cs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	665 "ne",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	666 "eq",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	667 "vc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	668 "vs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	669 "pl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	670 "mi",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	671 "ge",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	672 "lt",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	673 "gt",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	674 "le"
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	675 };
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	676
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	677 int m68K_disasm_op(m68k_op_info decoded, uint8_t size, char dst, int need_comma)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	678 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	679 char * c = need_comma ? "," : "";
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	680 switch(decoded->addr_mode)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	681 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	682 case MODE_REG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	683 return sprintf(dst, "%s d%d", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	684 case MODE_AREG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	685 return sprintf(dst, "%s a%d", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	686 case MODE_AREG_INDIRECT:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	687 return sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	688 case MODE_AREG_POSTINC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	689 return sprintf(dst, "%s (a%d)+", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	690 case MODE_AREG_PREDEC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	691 return sprintf(dst, "%s -(a%d)", c, decoded->params.regs.pri);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	692 case MODE_IMMEDIATE:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	693 return sprintf(dst, "%s #%d", c, size == OPSIZE_LONG ? decoded->params.u32 : (size == OPSIZE_WORD ? decoded->params.u16 : decoded->params.u8));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	694 default:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	695 return 0;
0 2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	696 }
2432d177e1ac Initial work on M68K instruction decoding Mike Pavone <pavone@retrodev.com> parents: diff changeset	697 }
2 5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	698
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	699 int m68k_disasm(m68kinst * decoded, char * dst)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	700 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	701 int ret,op1len;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	702 uint8_t size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	703 if (decoded->op == M68K_BCC \|\| decoded->op == M68K_DBCC \|\| decoded->op == M68K_SCC) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	704 ret = strlen(mnemonics[decoded->op]) - 2;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	705 memcpy(dst, mnemonics[decoded->op], ret);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	706 dst[ret] = 0;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	707 strcat(dst, cond_mnem[decoded->extra.cond]);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	708 ret = strlen(dst);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	709 size = decoded->op = M68K_BCC ? OPSIZE_LONG : OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	710 } else if (decoded->op == M68K_BSR) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	711 size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	712 ret = sprintf(dst, "bsr%s", decoded->variant == VAR_BYTE ? ".s" : "");
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	713 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	714 size = decoded->extra.size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	715 ret = sprintf(dst, "%s%s.%c",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	716 mnemonics[decoded->op],
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	717 decoded->variant == VAR_QUICK ? "q" : "",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	718 decoded->extra.size == OPSIZE_BYTE ? 'b' : (size == OPSIZE_WORD ? 'w' : 'l'));
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	719 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	720 op1len = m68K_disasm_op(&(decoded->src), size, dst + ret, 0);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	721 ret += op1len;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	722 ret += m68K_disasm_op(&(decoded->dst), size, dst + ret, op1len);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	723 return ret;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	724 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler. Mike Pavone <pavone@retrodev.com> parents: 0 diff changeset	725

Mercurial > repos > blastem

annotate 68kinst.c @ 6:b231162c8fdd