Mercurial > repos > blastem

annotate 68kinst.h @ 622:b76d2a628ab9

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
author Michael Pavone <pavone@retrodev.com>
date Tue, 17 Jun 2014 19:01:01 -0700
parents 775802dab98f
children 47123183c336
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
467
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents: 226
diff changeset
1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents: 226
diff changeset
2 Copyright 2013 Michael Pavone
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3 This file is part of BlastEm.
467
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents: 226
diff changeset
4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents: 226
diff changeset
5 */
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
6 #ifndef M68KINST_H_
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
7 #define M68KINST_H_
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
8
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
9 #include <stdint.h>
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
10
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
11 typedef enum {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
12 BIT_MOVEP_IMMED = 0,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
13 MOVE_BYTE,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
14 MOVE_LONG,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
15 MOVE_WORD,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
16 MISC,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
17 QUICK_ARITH_LOOP,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
18 BRANCH,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
19 MOVEQ,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
20 OR_DIV_SBCD,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
21 SUB_SUBX,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
22 RESERVED,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
23 CMP_XOR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
24 AND_MUL_ABCD_EXG,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
25 ADD_ADDX,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
26 SHIFT_ROTATE,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
27 COPROC
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
28 } m68k_optypes;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
29
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
30 typedef enum {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
31 M68K_ABCD,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
32 M68K_ADD,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
33 M68K_ADDX,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
34 M68K_AND,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
35 M68K_ANDI_CCR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
36 M68K_ANDI_SR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
37 M68K_ASL,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
38 M68K_ASR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
39 M68K_BCC,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
40 M68K_BCHG,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
41 M68K_BCLR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
42 M68K_BSET,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
43 M68K_BSR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
44 M68K_BTST,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
45 M68K_CHK,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
46 M68K_CLR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
47 M68K_CMP,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
48 M68K_DBCC,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
49 M68K_DIVS,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
50 M68K_DIVU,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
51 M68K_EOR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
52 M68K_EORI_CCR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
53 M68K_EORI_SR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
54 M68K_EXG,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
55 M68K_EXT,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
56 M68K_ILLEGAL,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
57 M68K_JMP,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
58 M68K_JSR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
59 M68K_LEA,
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
60 M68K_LINK,
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
61 M68K_LSL,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
62 M68K_LSR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
63 M68K_MOVE,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
64 M68K_MOVE_CCR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
65 M68K_MOVE_FROM_SR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
66 M68K_MOVE_SR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
67 M68K_MOVE_USP,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
68 M68K_MOVEM,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
69 M68K_MOVEP,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
70 M68K_MULS,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
71 M68K_MULU,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
72 M68K_NBCD,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
73 M68K_NEG,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
74 M68K_NEGX,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
75 M68K_NOP,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
76 M68K_NOT,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
77 M68K_OR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
78 M68K_ORI_CCR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
79 M68K_ORI_SR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
80 M68K_PEA,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
81 M68K_RESET,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
82 M68K_ROL,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
83 M68K_ROR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
84 M68K_ROXL,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
85 M68K_ROXR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
86 M68K_RTE,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
87 M68K_RTR,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
88 M68K_RTS,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
89 M68K_SBCD,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
90 M68K_SCC,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
91 M68K_STOP,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
92 M68K_SUB,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
93 M68K_SUBX,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
94 M68K_SWAP,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
95 M68K_TAS,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
96 M68K_TRAP,
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
97 M68K_TRAPV,
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
98 M68K_TST,
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
99 M68K_UNLK,
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
100 M68K_INVALID
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
101 } m68K_op;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
102
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
103 typedef enum {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
104 VAR_NORMAL,
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
105 VAR_QUICK,
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 2
diff changeset
106 VAR_IMMEDIATE,
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
107 VAR_BYTE,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
108 VAR_WORD,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
109 VAR_LONG
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
110 } m68K_variant;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
111
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
112 typedef enum {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
113 OPSIZE_BYTE=0,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
114 OPSIZE_WORD,
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
115 OPSIZE_LONG,
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
116 OPSIZE_INVALID,
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
117 OPSIZE_UNSIZED
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
118 } m68K_opsizes;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
119
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
120 typedef enum {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
121 //actual addressing mode field values
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
122 MODE_REG = 0,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
123 MODE_AREG,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
124 MODE_AREG_INDIRECT,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
125 MODE_AREG_POSTINC,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
126 MODE_AREG_PREDEC,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
127 MODE_AREG_DISPLACE,
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
128 MODE_AREG_INDEX_MEM, //bunch of relatively complicated modes
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
129 MODE_PC_INDIRECT_ABS_IMMED, //Modes that use the program counter, an absolute address or immediate value
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
130 //expanded values
79
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
131 MODE_AREG_INDEX_DISP8,
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
132 #ifdef M68020
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
133 MODE_AREG_INDEX_DISP32,
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
134 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
135 MODE_ABSOLUTE_SHORT,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
136 MODE_ABSOLUTE,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
137 MODE_PC_DISPLACE,
79
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
138 MODE_PC_INDEX_DISP8,
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
139 #ifdef M68020
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
140 MODE_PC_INDEX_DISP32,
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
141 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
142 MODE_IMMEDIATE,
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
143 MODE_IMMEDIATE_WORD,//used to indicate an immediate operand that only uses a single extension word even for a long operation
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
144 MODE_UNUSED
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
145 } m68k_addr_modes;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
146
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
147 typedef enum {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
148 COND_TRUE,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
149 COND_FALSE,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
150 COND_HIGH,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
151 COND_LOW_SAME,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
152 COND_CARRY_CLR,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
153 COND_CARRY_SET,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
154 COND_NOT_EQ,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
155 COND_EQ,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
156 COND_OVERF_CLR,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
157 COND_OVERF_SET,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
158 COND_PLUS,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
159 COND_MINUS,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
160 COND_GREATER_EQ,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
161 COND_LESS,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
162 COND_GREATER,
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
163 COND_LESS_EQ
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
164 } m68K_condition;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
165
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
166 typedef struct {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
167 uint8_t addr_mode;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
168 union {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
169 struct {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
170 uint8_t pri;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
171 uint8_t sec;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
172 int32_t displacement;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
173 } regs;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
174 uint32_t immed;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
175 } params;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
176 } m68k_op_info;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
177
208
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 134
diff changeset
178 typedef struct m68kinst {
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
179 uint8_t op;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
180 uint8_t variant;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
181 union {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
182 uint8_t size;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
183 uint8_t cond;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
184 } extra;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
185 uint32_t address;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
186 m68k_op_info src;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
187 m68k_op_info dst;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
188 } m68kinst;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
189
226
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
190 typedef enum {
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
191 VECTOR_RESET_STACK,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
192 VECTOR_RESET_PC,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
193 VECTOR_ACCESS_FAULT,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
194 VECTOR_ADDRESS_ERROR,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
195 VECTOR_ILLEGAL_INST,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
196 VECTOR_INT_DIV_ZERO,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
197 VECTOR_CHK,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
198 VECTOR_TRAPV,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
199 VECTOR_PRIV_VIOLATION,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
200 VECTOR_TRACE,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
201 VECTOR_LINE_1010,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
202 VECTOR_LINE_1111,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
203 VECTOR_COPROC_VIOLATION=13,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
204 VECTOR_FORMAT_ERROR,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
205 VECTOR_UNINIT_INTERRUPT,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
206 VECTOR_SPURIOUS_INTERRUPT=24,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
207 VECTOR_INT_1,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
208 VECTOR_INT_2,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
209 VECTOR_INT_3,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
210 VECTOR_INT_4,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
211 VECTOR_INT_5,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
212 VECTOR_INT_6,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
213 VECTOR_INT_7,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
214 VECTOR_TRAP_0,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
215 VECTOR_TRAP_1,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
216 VECTOR_TRAP_2,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
217 VECTOR_TRAP_3,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
218 VECTOR_TRAP_4,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
219 VECTOR_TRAP_5,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
220 VECTOR_TRAP_6,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
221 VECTOR_TRAP_7,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
222 VECTOR_TRAP_8,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
223 VECTOR_TRAP_9,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
224 VECTOR_TRAP_10,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
225 VECTOR_TRAP_11,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
226 VECTOR_TRAP_12,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
227 VECTOR_TRAP_13,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
228 VECTOR_TRAP_14,
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
229 VECTOR_TRAP_15
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
230 } m68k_vector;
28a6697e847b Implement CHK instruction (not fully tested).
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
231
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
232 uint16_t * m68k_decode(uint16_t * istream, m68kinst * dst, uint32_t address);
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
233 uint32_t m68k_branch_target(m68kinst * inst, uint32_t *dregs, uint32_t *aregs);
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
234 uint8_t m68k_is_branch(m68kinst * inst);
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
235 uint8_t m68k_is_noncall_branch(m68kinst * inst);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
236 int m68k_disasm(m68kinst * decoded, char * dst);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 79
diff changeset
237 int m68k_disasm_labels(m68kinst * decoded, char * dst);
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
238
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
239 #endif
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
240