Mercurial > repos > blastem

annotate gen_x86.h @ 622:b76d2a628ab9

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Partially working switch to having a vcounter and hslot counter in the context rather than trying to derive them from the cycle count. This should allow for more accurate handling of mid screen mode switches. Interrupt timing is broken currently though
author Michael Pavone <pavone@retrodev.com>
date Tue, 17 Jun 2014 19:01:01 -0700
parents 0bf5e6b672fe
children 96489fb27dbf
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
467
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents: 421
diff changeset
1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents: 421
diff changeset
2 Copyright 2013 Michael Pavone
484
0bf5e6b672fe Add support for test instruction to x86 generator library
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3 This file is part of BlastEm.
467
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents: 421
diff changeset
4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents: 421
diff changeset
5 */
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
6 #ifndef GEN_X86_H_
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
7 #define GEN_X86_H_
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
8
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
9 #include <stdint.h>
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
10
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
11 enum {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
12 RAX = 0,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
13 RCX,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
14 RDX,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
15 RBX,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
16 RSP,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
17 RBP,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
18 RSI,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
19 RDI,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
20 AH,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
21 CH,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
22 DH,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
23 BH,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
24 R8,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
25 R9,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
26 R10,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
27 R11,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
28 R12,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
29 R13,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
30 R14,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
31 R15
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
32 } x86_regs;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
33
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
34 enum {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
35 CC_O = 0,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
36 CC_NO,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
37 CC_C,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
38 CC_NC,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
39 CC_Z,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
40 CC_NZ,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
41 CC_BE,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
42 CC_A,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
43 CC_S,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
44 CC_NS,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
45 CC_P,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
46 CC_NP,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
47 CC_L,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
48 CC_GE,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
49 CC_LE,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
50 CC_G
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
51 } x86_cc;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
52
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
53 enum {
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
54 SZ_B = 0,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
55 SZ_W,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
56 SZ_D,
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
57 SZ_Q
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
58 } x86_size;
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
59
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
60 enum {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
61 MODE_REG_INDIRECT = 0,
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
62 MODE_REG_INDEXED = 4,
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
63 MODE_REG_DISPLACE8 = 0x40,
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
64 MODE_REG_INDEXED_DISPLACE8 = 0x44,
343
467bfa17004a Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
65 MODE_REG_DISPLACE32 = 0x80,
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
66 MODE_REG_INDEXED_DIPSLACE32 = 0x84,
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
67 MODE_REG_DIRECT = 0xC0,
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
68 //"phony" mode
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
69 MODE_IMMED = 0xFF
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
70 } x86_modes;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
71
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
72
49
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
73 uint8_t * rol_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
74 uint8_t * ror_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
75 uint8_t * rcl_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
76 uint8_t * rcr_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
77 uint8_t * shl_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
78 uint8_t * shr_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
79 uint8_t * sar_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
80 uint8_t * rol_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
81 uint8_t * ror_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
82 uint8_t * rcl_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
83 uint8_t * rcr_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
84 uint8_t * shl_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
85 uint8_t * shr_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
86 uint8_t * sar_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size);
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
87 uint8_t * rol_clr(uint8_t * out, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
88 uint8_t * ror_clr(uint8_t * out, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
89 uint8_t * rcl_clr(uint8_t * out, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
90 uint8_t * rcr_clr(uint8_t * out, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
91 uint8_t * shl_clr(uint8_t * out, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
92 uint8_t * shr_clr(uint8_t * out, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
93 uint8_t * sar_clr(uint8_t * out, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
94 uint8_t * rol_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
95 uint8_t * ror_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
96 uint8_t * rcl_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
97 uint8_t * rcr_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
98 uint8_t * shl_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
99 uint8_t * shr_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 49
diff changeset
100 uint8_t * sar_clrdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
101 uint8_t * add_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
102 uint8_t * adc_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
103 uint8_t * or_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
104 uint8_t * xor_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
105 uint8_t * and_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
106 uint8_t * sub_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
107 uint8_t * sbb_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
108 uint8_t * cmp_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
109 uint8_t * add_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
110 uint8_t * adc_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
111 uint8_t * or_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size);
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
112 uint8_t * xor_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size);
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
113 uint8_t * and_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size);
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
114 uint8_t * sub_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
115 uint8_t * sbb_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
116 uint8_t * cmp_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
117 uint8_t * add_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size);
421
d0cacb4ade0b Move IO code to a separate file and do a tiny bit of refactoring
Mike Pavone <pavone@retrodev.com>
parents: 343
diff changeset
118 uint8_t * add_irdisp32(uint8_t * out, int32_t val, uint8_t dst_base, int32_t disp, uint8_t size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
119 uint8_t * adc_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
120 uint8_t * or_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
121 uint8_t * xor_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
122 uint8_t * and_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
123 uint8_t * sub_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
124 uint8_t * sbb_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
125 uint8_t * cmp_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
126 uint8_t * add_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
127 uint8_t * adc_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
128 uint8_t * add_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
129 uint8_t * adc_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
130 uint8_t * or_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
131 uint8_t * or_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
132 uint8_t * xor_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
133 uint8_t * xor_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
134 uint8_t * and_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
135 uint8_t * and_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
136 uint8_t * sub_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
137 uint8_t * sub_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size);
146
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
138 uint8_t * sbb_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size);
5416a5c4628e Implement most of the "X" instructions
Mike Pavone <pavone@retrodev.com>
parents: 123
diff changeset
139 uint8_t * sbb_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
140 uint8_t * cmp_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
141 uint8_t * cmp_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size);
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
142 uint8_t * imul_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
143 uint8_t * imul_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
144 uint8_t * imul_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size);
82
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
145 uint8_t * not_r(uint8_t * out, uint8_t dst, uint8_t size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
146 uint8_t * neg_r(uint8_t * out, uint8_t dst, uint8_t size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
147 uint8_t * not_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Mike Pavone <pavone@retrodev.com>
parents: 81
diff changeset
148 uint8_t * neg_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size);
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
149 uint8_t * mul_r(uint8_t * out, uint8_t dst, uint8_t size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
150 uint8_t * imul_r(uint8_t * out, uint8_t dst, uint8_t size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
151 uint8_t * div_r(uint8_t * out, uint8_t dst, uint8_t size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
152 uint8_t * idiv_r(uint8_t * out, uint8_t dst, uint8_t size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
153 uint8_t * mul_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
154 uint8_t * imul_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
155 uint8_t * div_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
156 uint8_t * idiv_rdisp8(uint8_t * out, uint8_t dst_base, int8_t disp, uint8_t size);
484
0bf5e6b672fe Add support for test instruction to x86 generator library
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
157 uint8_t * test_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
0bf5e6b672fe Add support for test instruction to x86 generator library
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
158 uint8_t * test_ir(uint8_t * out, int32_t val, uint8_t dst, uint8_t size);
0bf5e6b672fe Add support for test instruction to x86 generator library
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
159 uint8_t * test_irdisp8(uint8_t * out, int32_t val, uint8_t dst_base, int8_t disp, uint8_t size);
0bf5e6b672fe Add support for test instruction to x86 generator library
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
160 uint8_t * test_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size);
0bf5e6b672fe Add support for test instruction to x86 generator library
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
161 uint8_t * test_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
162 uint8_t * mov_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
163 uint8_t * mov_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t disp, uint8_t size);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
164 uint8_t * mov_rdisp8r(uint8_t * out, uint8_t src_base, int8_t disp, uint8_t dst, uint8_t size);
343
467bfa17004a Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
165 uint8_t * mov_rrdisp32(uint8_t * out, uint8_t src, uint8_t dst_base, int32_t disp, uint8_t size);
467bfa17004a Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
166 uint8_t * mov_rdisp32r(uint8_t * out, uint8_t src_base, int32_t disp, uint8_t dst, uint8_t size);
467bfa17004a Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
167 uint8_t * mov_rrindex(uint8_t * out, uint8_t src, uint8_t dst_base, uint8_t dst_index, uint8_t scale, uint8_t size);
467bfa17004a Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
168 uint8_t * mov_rindexr(uint8_t * out, uint8_t src_base, uint8_t src_index, uint8_t scale, uint8_t dst, uint8_t size);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
169 uint8_t * mov_rrind(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
170 uint8_t * mov_rindr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 14
diff changeset
171 uint8_t * mov_ir(uint8_t * out, int64_t val, uint8_t dst, uint8_t size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
172 uint8_t * mov_irdisp8(uint8_t * out, int32_t val, uint8_t dst, int8_t disp, uint8_t size);
71
f80fa1776507 Implement more instructions and address modes
Mike Pavone <pavone@retrodev.com>
parents: 61
diff changeset
173 uint8_t * mov_irind(uint8_t * out, int32_t val, uint8_t dst, uint8_t size);
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
174 uint8_t * movsx_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t src_size, uint8_t size);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
175 uint8_t * movsx_rdisp8r(uint8_t * out, uint8_t src, int8_t disp, uint8_t dst, uint8_t src_size, uint8_t size);
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
176 uint8_t * movzx_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t src_size, uint8_t size);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
177 uint8_t * movzx_rdisp8r(uint8_t * out, uint8_t src, int8_t disp, uint8_t dst, uint8_t src_size, uint8_t size);
241
2586d49ddd46 Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents: 207
diff changeset
178 uint8_t * xchg_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
179 uint8_t * pushf(uint8_t * out);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
180 uint8_t * popf(uint8_t * out);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
181 uint8_t * push_r(uint8_t * out, uint8_t reg);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
182 uint8_t * pop_r(uint8_t * out, uint8_t reg);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
183 uint8_t * setcc_r(uint8_t * out, uint8_t cc, uint8_t dst);
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
184 uint8_t * setcc_rind(uint8_t * out, uint8_t cc, uint8_t dst);
112
e3594572fb98 Implement scc (untested)
Mike Pavone <pavone@retrodev.com>
parents: 82
diff changeset
185 uint8_t * setcc_rdisp8(uint8_t * out, uint8_t cc, uint8_t dst, int8_t disp);
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
186 uint8_t * bt_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
187 uint8_t * bt_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t dst_disp, uint8_t size);
343
467bfa17004a Mostly working runtime generation of memory map read/write functions
Mike Pavone <pavone@retrodev.com>
parents: 241
diff changeset
188 uint8_t * bt_rrdisp32(uint8_t * out, uint8_t src, uint8_t dst_base, int32_t dst_disp, uint8_t size);
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
189 uint8_t * bt_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
190 uint8_t * bt_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t dst_disp, uint8_t size);
123
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 112
diff changeset
191 uint8_t * bts_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 112
diff changeset
192 uint8_t * bts_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t dst_disp, uint8_t size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 112
diff changeset
193 uint8_t * bts_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 112
diff changeset
194 uint8_t * bts_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t dst_disp, uint8_t size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 112
diff changeset
195 uint8_t * btr_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 112
diff changeset
196 uint8_t * btr_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t dst_disp, uint8_t size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 112
diff changeset
197 uint8_t * btr_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 112
diff changeset
198 uint8_t * btr_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t dst_disp, uint8_t size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 112
diff changeset
199 uint8_t * btc_rr(uint8_t * out, uint8_t src, uint8_t dst, uint8_t size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 112
diff changeset
200 uint8_t * btc_rrdisp8(uint8_t * out, uint8_t src, uint8_t dst_base, int8_t dst_disp, uint8_t size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 112
diff changeset
201 uint8_t * btc_ir(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size);
bd3858121ab0 Implement the rest of the bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 112
diff changeset
202 uint8_t * btc_irdisp8(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t dst_disp, uint8_t size);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
203 uint8_t * jcc(uint8_t * out, uint8_t cc, uint8_t *dest);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
204 uint8_t * jmp(uint8_t * out, uint8_t *dest);
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
205 uint8_t * jmp_r(uint8_t * out, uint8_t dst);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
206 uint8_t * call(uint8_t * out, uint8_t * fun);
81
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Mike Pavone <pavone@retrodev.com>
parents: 71
diff changeset
207 uint8_t * call_r(uint8_t * out, uint8_t dst);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
208 uint8_t * retn(uint8_t * out);
151
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents: 146
diff changeset
209 uint8_t * cdq(uint8_t * out);
207
c82f65a87a53 Fix overflow flag on ASL
Mike Pavone <pavone@retrodev.com>
parents: 151
diff changeset
210 uint8_t * loop(uint8_t * out, uint8_t * dst);
14
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
211
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
212 #endif //GEN_X86_H_
2bdad0f52f42 x86 code gen, initial work on translator
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
213