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annotate analyze.py @ 989:d70000fdff0b

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Implemented IR and undefined bits of info word for address error exception frames
author Michael Pavone <pavone@retrodev.com>
date Wed, 27 Apr 2016 21:39:17 -0700
parents 006008a3f370
children
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1 #!/usr/bin/env python
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2
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3 #OLD
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4 #0 - !SE
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5 #1 - !CAS
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6 #2 - A0
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7 #3 - A1
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8 #------
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9 #4 - A2
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10 #5 - A3
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11 #6 - A7
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12 #7 - EDCLK
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13 #------
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14 #8 - !HSYNC
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15 #9 - A4
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16 #A - A5
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17 #B - A6
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18 #------
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19 #C - !RAS
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20 #D - !WB/!WE
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21 #E - !DT/!OE
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22 #F - SC
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24 #NEW
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25 #0 - !IPL2
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26 #1 - !CAS
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27 #2 - A0
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28 #3 - A1
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29 #------
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30 #4 - A2
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33 #7 - !HSYNC
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34 #------
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35 #8 - !VSYNC
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36 #9 - A4
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37 #A - A5
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38 #B - A6
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39 #------
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40 #C - !RAS
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41 #D - !WB/!WE
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42 #E - !DT/!OE
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43 #F - SC
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46 #VRAM swizzling
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47 #A0 = V0
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48 #A1 = V1
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49 #A8 = V2
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50 #A9 = V3
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51 #A10 = V4
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52 #A11 = V5
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53 #A12 = V6
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54 #A13 = V7
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55 #A14 = V8
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56 #A15 = V9
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57 #--guesses follow--
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58 #A2 = V10
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59 #A3 = V11
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60 #A4 = V12
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61 #A5 = V13
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62 #A6 = V14
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63 #A7 = V15
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66 def get_addr(sample):
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67 return ((sample >> 2) & 0xF) | ((sample >> 5) & 0x70) | ((sample << 1) & 0x80)
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68
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69 def swizzle_addr(addr):
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70 return (addr & 0x0003) | ((addr >> 6) & 0x03FC) | ((addr << 8) & 0xFC00)
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71
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72 def print_addr_op(addr, addr_format, mode, samplenum, triggerpos, rate):
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73 print '{0:{1}} ({2:{1}}) {3}@{4} ns'.format(swizzle_addr(addr), addr_format, addr, mode, (samplenum - triggerpos)*rate)
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74
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75 def detect_rise(last, sample, bit):
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76 mask = 1 << bit
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77 return (not last & mask) and (sample & mask)
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78
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79 def detect_fall(last, sample, bit):
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80 mask = 1 << bit
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81 return (last & mask) and (not sample & mask)
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82
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83 def detect_high(sample, bit):
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84 mask = 1 << bit
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85 return sample & mask
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86
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87
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88 ipl2 = 0x0
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89 cas = 0x1
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90 ras = 0xC
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91 vsync = 0x8
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92 hsync = 0x7
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93 wewb = 0xD
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94 oedt = 0xE
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95 sc = 0xF
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96
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97 last = False
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98 state = 'begin'
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99 triggerpos = 0
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100 readcounter = 0
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101 sillyread = 0
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102 lastaddr = -1
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103 edclk_ticks = 0
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104 sc_ticks = 0
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105 tick_start = False
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106 #f = open('street_fighter_vram_100mhz_hsync_trig_2.ols')
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107 #f = open('street_fighter_vram_50mhz_hsync_trig.ols')
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108 from sys import argv,exit
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109 if len(argv) < 2:
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110 print 'usage: analyze.py filename'
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111 exit(1)
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112 if '-b' in argv:
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113 addr_format = '016b'
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114 else:
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115 addr_format = '04X'
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116 f = open(argv[1])
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117 for line in f:
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118 if line.startswith(';TriggerPosition'):
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119 _,_,triggerpos = line.partition(':')
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120 triggerpos = int(triggerpos.strip())
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121 elif line.startswith(';Rate'):
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122 _,_,rate = line.partition(':')
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123 #convert to nanoseconds between samples
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124 rate = (1.0/float(rate.strip())) * 1000000000.0
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125 elif not line.startswith(';'):
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126 sample,_,samplenum = line.partition('@')
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127 samplenum = int(samplenum.strip())
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128 sample = int(sample, 16)
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129 if detect_rise(last, sample, sc):
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130 sc_ticks += 1
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131 if not (last is False):
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132 #detect falling edge of !HSYNC
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133 if detect_fall(last, sample, hsync):
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134 if readcounter:
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135 print readcounter, 'reads,', sillyread, 'redundant reads'
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136 readcounter = sillyread = 0
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137 if not tick_start is False:
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138 print 'SC:', sc_ticks, ' ticks, {0}MHz'.format(float(sc_ticks)/((rate * (samplenum-tick_start)) / 1000.0))
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139 tick_start = samplenum
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140 edclk_ticks = sc_ticks = 0
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141 print 'HSYNC Start @ {0} ns'.format((samplenum - triggerpos)*rate)
6
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142 #detect rising edge of !HSYNC
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143 elif detect_rise(last, sample, hsync):
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144 if not tick_start is False:
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145 float(edclk_ticks)/((rate * (samplenum-tick_start)) / 1000.0)
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146 print 'EDCLK:', edclk_ticks, ' ticks, {0}MHz'.format(float(edclk_ticks)/((rate * (samplenum-tick_start)) / 1000.0))
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147 print 'SC:', sc_ticks, ' ticks, {0}MHz'.format(float(sc_ticks)/((rate * (samplenum-tick_start)) / 1000.0))
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148 tick_start = samplenum
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149 edclk_ticks = sc_ticks = 0
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150 print 'HSYNC End @ {0} ns'.format((samplenum - triggerpos)*rate)
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151 if detect_fall(last, sample, vsync):
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152 print 'VSYNC Start @ {0} ns'.format((samplenum - triggerpos)*rate)
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153 elif detect_rise(last, sample, vsync):
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154 print 'VSYNC End @ {0} ns'.format((samplenum - triggerpos)*rate)
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155 if detect_fall(last, sample, ipl2):
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156 print 'IPL2 Low @ {0} ns'.format((samplenum - triggerpos)*rate)
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157 elif detect_rise(last, sample, ipl2):
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158 print 'IPL2 High @ {0} ns'.format((samplenum - triggerpos)*rate)
6
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159 if state == 'begin':
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160 #detect falling edge of !RAS
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161 if detect_fall(last, sample, ras):
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162 state = 'ras'
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163 row = get_addr(sample)
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164 mode = 'ram' if detect_high(sample, oedt) else 'read transfer'
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165 elif detect_fall(last, sample, cas) and detect_high(sample, oedt):
6
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166 state = 'cas'
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167 elif state == 'ras':
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168 if detect_fall(last, sample, cas):
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169 state = 'begin'
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170 col = get_addr(sample)
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171 addr = (row << 8) | col
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172 if mode == 'ram':
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173 state = 'ras_cas'
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174 else:
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175 print_addr_op(addr, addr_format, mode, samplenum, triggerpos, rate)
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176 lastaddr = addr
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177 #print '{0:04X} {1} - {2:02X}:{3:02X} - {0:016b}'.format(addr, mode, row, col)
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178 elif state == 'cas':
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179 if detect_fall(last, sample, ras):
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180 state = 'begin'
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181 print 'refresh@{0} ns'.format((samplenum - triggerpos)*rate)
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182 elif state == 'ras_cas':
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183 if detect_fall(last, sample, oedt):
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184 readcounter += 1
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185 if addr == lastaddr:
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186 sillyread += 1
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187 print_addr_op(addr, addr_format, 'read', samplenum, triggerpos, rate)
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188 state = 'begin'
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189 elif detect_fall(last, sample, wewb):
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190 print_addr_op(addr, addr_format, 'write', samplenum, triggerpos, rate)
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191 state = 'begin'
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192 last = sample