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annotate segacd.h @ 2068:f573f2c31bc9 segacd

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Dump PROG RAM to file for debugging
author Michael Pavone <pavone@retrodev.com>
date Sun, 30 Jan 2022 11:58:34 -0800
parents a61a8a87410c
children 8e51c0c3f2e3
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
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1 #ifndef SEGACD_H_
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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parents: 1467
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2 #define SEGACD_H_
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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3 #include <stdint.h>
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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4 #include "genesis.h"
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70260f6051dd Initial work on CDC emulation
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5 #include "lc8951.h"
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
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parents: 2058
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6 #include "cdd_mcu.h"
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2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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parents: 1467
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7
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
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8 typedef struct {
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Michael Pavone <pavone@retrodev.com>
parents: 1503
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9 m68k_context *m68k;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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parents: 1503
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10 system_media *media;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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11 genesis_context *genesis;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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12 uint16_t gate_array[0x100];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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13 uint16_t *rom; //unaltered ROM, needed for mirrored locations
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
diff changeset
14 uint16_t *rom_mut; //ROM with low 16-bit of HINT vector modified by register write
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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15 uint16_t *prog_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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16 uint16_t *word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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17 uint8_t *pcm_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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18 uint8_t *bram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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19 uint32_t stopwatch_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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20 uint32_t int2_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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21 uint32_t periph_reset_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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22 uint32_t base;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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23 uint8_t timer_pending;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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24 uint8_t timer_value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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25 uint8_t busreq;
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Michael Pavone <pavone@retrodev.com>
parents: 1503
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26 uint8_t busack;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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27 uint8_t reset;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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28 uint8_t need_reset;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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29 uint8_t memptr_start_index;
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2054
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30 lc8951 cdc;
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
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31 cdd_mcu cdd;
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2061
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32 uint8_t cdc_dst_low;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
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33 uint8_t cdc_int_ack;
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
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34 } segacd_context;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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35
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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parents: 1467
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36 segacd_context *alloc_configure_segacd(system_media *media, uint32_t opts, uint8_t force_region, rom_info *info);
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8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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37 memmap_chunk *segacd_main_cpu_map(segacd_context *cd, uint8_t cart_boot, uint32_t *num_chunks);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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38 uint32_t gen_cycle_to_scd(uint32_t cycle, genesis_context *gen);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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39 void scd_run(segacd_context *cd, uint32_t cycle);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1503
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40 void scd_adjust_cycle(segacd_context *cd, uint32_t deduction);
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
41
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
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42 #endif //SEGACD_H_