repos/blastem: cpu_dsl.py annotate

annotate cpu_dsl.py @ 2707:a64c0e1ed6ac default tip

Implement speed control and reset for media player. Fix other bindings that could cause it to crash

author	Michael Pavone <pavone@retrodev.com>
date	Sun, 06 Jul 2025 20:43:37 -0700
parents	c5dce4284e69
children

rev	line source
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1 #!/usr/bin/env python3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2
2440 338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	3 assignmentOps = {
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	4 '=': 'mov',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	5 '+=': 'add',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	6 '-=': 'sub',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	7 '<<=': 'lsl',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	8 '>>=': 'lsr',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	9 '&=': 'and',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	10 '\|=': 'or',
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	11 '^=': 'xor'
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	12 }
2441 4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	13 binaryOps = {
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	14 '+': 'add',
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	15 '-': 'sub',
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	16 '<<': 'lsl',
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	17 '>>': 'lsr',
2562 595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	18 '*': 'mulu',
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	19 '*S': 'muls',
2441 4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	20 '&': 'and',
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	21 '\|': 'or',
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	22 '^': 'xor'
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	23 }
2443 461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	24 unaryOps = {
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	25 '~': 'not',
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	26 '!': 'lnot',
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	27 '-': 'neg'
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	28 }
2442 52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	29 compareOps = {'>=U', '=', '!='}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	30 class Block:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	31 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	32 pass
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	33
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	34 def processLine(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	35 if parts[0] == 'switch':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	36 o = Switch(self, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	37 self.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	38 return o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	39 elif parts[0] == 'if':
2442 52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	40 if len(parts) == 4 and parts[2] in compareOps:
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	41 self.addOp(NormalOp(['cmp', parts[3], parts[1]]))
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	42 cond = parts[2]
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	43 else:
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	44 cond = parts[1]
52cfc7b14dd2 Sugar for some basic conditionals in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2441 diff changeset	45 o = If(self, cond)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	46 self.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	47 return o
2618 1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	48 elif parts[0] == 'loop':
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	49 o = Loop(self, None if len(parts) == 1 else parts[1])
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	50 self.addOp(o)
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	51 return o
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	52 elif parts[0] == 'end':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	53 raise Exception('end is only allowed inside a switch or if block')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	54 else:
2440 338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	55 if len(parts) > 1 and parts[1] in assignmentOps:
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	56 dst = parts[0]
2448 d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	57 dst,_,size = dst.partition(':')
2440 338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	58 op = parts[1]
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	59 parts = [assignmentOps[op]] + parts[2:]
2441 4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	60 if op == '=':
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	61 if len(parts) > 2 and parts[2] in binaryOps:
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	62 op = parts[2]
2478 ea37200967c7 Implement lea and pea in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2468 diff changeset	63 if op == '-':
ea37200967c7 Implement lea and pea in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2468 diff changeset	64 tmp = parts[1]
ea37200967c7 Implement lea and pea in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2468 diff changeset	65 parts[1] = parts[3]
ea37200967c7 Implement lea and pea in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2468 diff changeset	66 parts[3] = tmp
2441 4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	67 parts[0] = binaryOps[op]
4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	68 del parts[2]
2443 461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	69 elif len(parts) > 1 and parts[1][0] in unaryOps:
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	70 rest = parts[1][1:]
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	71 op = parts[1][0]
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	72 if rest:
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	73 parts[1] = rest
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	74 else:
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	75 del parts[1]
461fffc226e0 Sugar for unary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2442 diff changeset	76 parts[0] = unaryOps[op]
2441 4435abe5db5e Sugar for binary operators in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2440 diff changeset	77 else:
2440 338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	78 if op == '<<=' or op == '>>=':
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	79 parts.insert(1, dst)
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	80 else:
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	81 parts.append(dst)
338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	82 parts.append(dst)
2448 d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	83 if size:
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	84 parts.append(size)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	85 self.addOp(NormalOp(parts))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	86 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	87
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	88 def processOps(self, prog, fieldVals, output, otype, oplist):
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	89 for i in range(0, len(oplist)):
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	90 if i + 1 < len(oplist) and oplist[i+1].op == 'update_flags':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	91 flagUpdates, _ = prog.flags.parseFlagUpdate(oplist[i+1].params[0])
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	92 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	93 flagUpdates = None
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	94 oplist[i].generate(prog, self, fieldVals, output, otype, flagUpdates)
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	95
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	96 def processDispatch(self, prog):
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	97 for op in self.implementation:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	98 op.processDispatch(prog)
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	99
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	100 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	101 return None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	102
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	103 class ChildBlock(Block):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	104 def processLine(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	105 if parts[0] == 'end':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	106 return self.parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	107 return super().processLine(parts)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	108
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	109 #Represents an instruction of the emulated CPU
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	110 class Instruction(Block):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	111 def __init__(self, value, fields, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	112 self.value = value
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	113 self.fields = fields
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	114 self.name = name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	115 self.implementation = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	116 self.locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	117 self.regValues = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	118 self.varyingBits = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	119 self.invalidFieldValues = {}
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	120 self.invalidCombos = []
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	121 self.newLocals = []
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	122 self.noSpecialize = set()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	123 for field in fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	124 self.varyingBits += fields[field][1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	125
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	126 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	127 if op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	128 name = op.params[0]
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	129 size = int(op.params[1])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	130 self.locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	131 elif op.op == 'invalid':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	132 if len(op.params) < 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	133 name = op.params[0]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	134 value = int(op.params[1])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	135 self.invalidFieldValues.setdefault(name, set()).add(value)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	136 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	137 vmap = {}
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	138 for i in range(0, len(op.params), 2):
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	139 name = op.params[i]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	140 value = int(op.params[i+1])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	141 vmap[name] = value
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	142 self.invalidCombos.append(vmap)
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	143 elif op.op == 'nospecialize':
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	144 for name in op.params:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	145 self.noSpecialize.add(name)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	146 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	147 self.implementation.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	148
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	149 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	150 if name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	151 return name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	152 return None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	153
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	154 def addLocal(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	155 self.locals[name] = size
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	156 self.newLocals.append(name)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	157
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	158 def localSize(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	159 return self.locals.get(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	160
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	161 def __lt__(self, other):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	162 if isinstance(other, Instruction):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	163 if self.varyingBits != other.varyingBits:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	164 return self.varyingBits < other.varyingBits
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	165 return self.value < other.value
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	166 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	167 return NotImplemented
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	168
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	169 def allValues(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	170 values = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	171 for i in range(0, 1 << self.varyingBits):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	172 iword = self.value
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	173 doIt = True
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	174 combos = []
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	175 for combo in self.invalidCombos:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	176 combos.append(dict(combo))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	177 for field in self.fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	178 shift,bits = self.fields[field]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	179 val = i & ((1 << bits) - 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	180 if field in self.invalidFieldValues and val in self.invalidFieldValues[field]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	181 doIt = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	182 break
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	183 nextcombos = []
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	184 for combo in combos:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	185 if field in combo:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	186 if combo[field] == val:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	187 del combo[field]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	188 if not combo:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	189 doIt = False
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	190 break
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	191 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	192 continue
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	193 nextcombos.append(combo)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	194 combos = nextcombos
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	195 if not doIt:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	196 break
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	197 i >>= bits
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	198 iword \|= val << shift
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	199 if doIt:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	200 values.append(iword)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	201 return values
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	202
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	203 def getFieldVals(self, value):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	204 fieldVals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	205 fieldBits = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	206 for field in self.fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	207 shift,bits = self.fields[field]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	208 val = (value >> shift) & ((1 << bits) - 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	209 fieldVals[field] = val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	210 fieldBits[field] = bits
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	211 return (fieldVals, fieldBits)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	212
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	213 def generateName(self, value):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	214 fieldVals,fieldBits = self.getFieldVals(value)
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	215 for name in self.noSpecialize:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	216 del fieldVals[name]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	217 names = list(fieldVals.keys())
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	218 names.sort()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	219 funName = self.name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	220 for name in names:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	221 funName += '_{0}_{1:0>{2}}'.format(name, bin(fieldVals[name])[2:], fieldBits[name])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	222 return funName
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	223
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	224 def generateBody(self, value, prog, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	225 output = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	226 prog.meta = {}
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	227 prog.pushScope(self)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	228 self.regValues = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	229 for var in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	230 output.append('\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	231 self.newLocals = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	232 fieldVals,_ = self.getFieldVals(value)
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	233 for name in self.noSpecialize:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	234 del fieldVals[name]
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	235 self.locals[name] = prog.opsize
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	236 if len(prog.mainDispatch) != 1:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	237 raise Exception('nospecialize requires exactly 1 field used for main table dispatch')
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	238 shift,bits = self.fields[name]
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	239 mask = (1 << bits) - 1
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	240 opfield = list(prog.mainDispatch)[0]
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	241 if shift:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	242 output.append(f'\n\tuint{prog.opsize}_t {name} = context->{opfield} >> {shift} & {mask};')
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	243 else:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	244 output.append(f'\n\tuint{prog.opsize}_t {name} = context->{opfield} & {mask};')
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	245 self.processOps(prog, fieldVals, output, otype, self.implementation)
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	246 for name in self.noSpecialize:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	247 del self.locals[name]
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	248
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	249 if prog.dispatch == 'call':
2600 251cc75574af Basic emscripten support Michael Pavone <pavone@retrodev.com> parents: 2599 diff changeset	250 begin = '\nstatic void ' + self.generateName(value) + '(' + prog.context_type + ' *context, uint32_t target_cycle)\n{'
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	251 elif prog.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	252 begin = '\n' + self.generateName(value) + ': {'
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	253 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	254 raise Exception('Unsupported dispatch type ' + prog.dispatch)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	255 if prog.needFlagCoalesce:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	256 begin += prog.flags.coalesceFlags(prog, otype)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	257 if prog.needFlagDisperse:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	258 output.append(prog.flags.disperseFlags(prog, otype))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	259 for var in self.newLocals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	260 begin += '\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	261 for size in prog.temp:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	262 begin += '\n\tuint{sz}_t gen_tmp{sz}__;'.format(sz=size)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	263 prog.popScope()
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	264 if prog.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	265 output += prog.nextInstruction(otype)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	266 return begin + ''.join(output) + '\n}'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	267
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	268 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	269 pieces = [self.name + ' ' + hex(self.value) + ' ' + str(self.fields)]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	270 for name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	271 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	272 for op in self.implementation:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	273 pieces.append(str(op))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	274 return ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	275
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	276 #Represents the definition of a helper function
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	277 class SubRoutine(Block):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	278 def __init__(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	279 self.name = name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	280 self.implementation = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	281 self.args = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	282 self.arg_map = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	283 self.locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	284 self.regValues = {}
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	285 self.argValues = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	286
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	287 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	288 if op.op == 'arg':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	289 name = op.params[0]
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	290 size = int(op.params[1])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	291 self.arg_map[name] = len(self.args)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	292 self.args.append((name, size))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	293 elif op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	294 name = op.params[0]
1734 88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1733 diff changeset	295 size = int(op.params[1])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	296 self.locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	297 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	298 self.implementation.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	299
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	300 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	301 if name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	302 return self.name + '_' + name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	303 return None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	304
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	305 def addLocal(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	306 self.locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	307
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	308 def localSize(self, name):
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	309 if name in self.locals:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	310 return self.locals[name]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	311 if name in self.arg_map:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	312 argIndex = self.arg_map[name]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	313 return self.args[argIndex][1]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	314 return None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	315
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	316 def inline(self, prog, params, output, otype, parent):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	317 if len(params) != len(self.args):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	318 raise Exception('{0} expects {1} arguments, but was called with {2}'.format(self.name, len(self.args), len(params)))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	319 argValues = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	320 if parent:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	321 self.regValues = parent.regValues
2704 c5dce4284e69 Fix a couple of bugs in CPU DSL found while working on uPD78K/II core Michael Pavone <pavone@retrodev.com> parents: 2680 diff changeset	322 output.append('\n\t{')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	323 prog.pushScope(self)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	324 i = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	325 for name,size in self.args:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	326 argValues[name] = params[i]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	327 i += 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	328 for name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	329 size = self.locals[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	330 output.append('\n\tuint{size}_t {sub}_{local};'.format(size=size, sub=self.name, local=name))
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	331 self.argValues = argValues
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	332 self.processOps(prog, argValues, output, otype, self.implementation)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	333 prog.popScope()
2704 c5dce4284e69 Fix a couple of bugs in CPU DSL found while working on uPD78K/II core Michael Pavone <pavone@retrodev.com> parents: 2680 diff changeset	334 output.append('\n\t}')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	335
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	336 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	337 pieces = [self.name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	338 for name,size in self.args:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	339 pieces.append('\n\targ {0} {1}'.format(name, size))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	340 for name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	341 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	342 for op in self.implementation:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	343 pieces.append(str(op))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	344 return ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	345
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	346 class Op:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	347 def __init__(self, evalFun = None):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	348 self.evalFun = evalFun
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	349 self.impls = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	350 self.outOp = ()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	351 def cBinaryOperator(self, op):
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	352 def _impl(prog, params, rawParams, flagUpdates):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	353 if op == '-':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	354 a = params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	355 b = params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	356 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	357 a = params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	358 b = params[1]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	359 needsSizeAdjust = False
2609 fbb5115b1a27 Fix issues in CPU DSL that caused regressions in Z80 core Michael Pavone <pavone@retrodev.com> parents: 2600 diff changeset	360 destSize = prog.paramSize(rawParams[2])
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	361 if len(params) > 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	362 size = params[3]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	363 if size == 0:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	364 size = 8
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	365 elif size == 1:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	366 size = 16
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	367 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	368 size = 32
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	369 if destSize > size:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	370 needsSizeAdjust = True
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	371 prog.sizeAdjust = size
2609 fbb5115b1a27 Fix issues in CPU DSL that caused regressions in Z80 core Michael Pavone <pavone@retrodev.com> parents: 2600 diff changeset	372 else:
fbb5115b1a27 Fix issues in CPU DSL that caused regressions in Z80 core Michael Pavone <pavone@retrodev.com> parents: 2600 diff changeset	373 size = destSize
fbb5115b1a27 Fix issues in CPU DSL that caused regressions in Z80 core Michael Pavone <pavone@retrodev.com> parents: 2600 diff changeset	374 prog.lastSize = size
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	375 needsCarry = needsOflow = needsHalf = False
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	376 if flagUpdates:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	377 for flag in flagUpdates:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	378 calc = prog.flags.flagCalc[flag]
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	379 if calc == 'carry':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	380 needsCarry = True
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	381 elif calc == 'half-carry':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	382 needsHalf = True
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	383 elif calc == 'overflow':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	384 needsOflow = True
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	385 decl = ''
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	386 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
2448 d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	387 if needsCarry and op != '>>':
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	388 size *= 2
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	389 decl,name = prog.getTemp(size)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	390 dst = prog.carryFlowDst = name
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	391 prog.lastA = a
1708 5bfed2eedc9d Fixed flag calculation for sub instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1707 diff changeset	392 prog.lastB = b
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	393 if size == 64:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	394 a = '((uint64_t){a})'.format(a=a)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	395 b = '((uint64_t){b})'.format(b=b)
1711 87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	396 prog.lastBFlow = b if op == '-' else '(~{b})'.format(b=b)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	397 elif needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	398 decl,name = prog.getTemp(size)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	399 dst = params[2]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	400 return '{decl}\n\t{tmp} = ({a} & {mask}) {op} ({b} & {mask});\n\t{dst} = ({dst} & ~{mask}) \| {tmp};'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	401 decl = decl, tmp = name, a = a, b = b, op = op, dst = dst, mask = ((1 << size) - 1)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	402 )
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	403 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	404 dst = params[2]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	405 if needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	406 return decl + '\n\t{dst} = ({a} & {mask}) {op} ({b} & {mask});'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	407 dst = dst, a = a, b = b, op = op, mask = (1 << prog.sizeAdjust) - 1
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	408 )
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	409 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	410 return decl + '\n\t{dst} = {a} {op} {b};'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	411 dst = dst, a = a, b = b, op = op
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	412 )
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	413 self.impls['c'] = _impl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	414 self.outOp = (2,)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	415 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	416 def cUnaryOperator(self, op):
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	417 def _impl(prog, params, rawParams, flagUpdates):
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	418 dst = params[1]
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	419 decl = ''
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	420 needsSizeAdjust = False
2609 fbb5115b1a27 Fix issues in CPU DSL that caused regressions in Z80 core Michael Pavone <pavone@retrodev.com> parents: 2600 diff changeset	421 destSize = prog.paramSize(rawParams[1])
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	422 if len(params) > 2:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	423 size = params[2]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	424 if size == 0:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	425 size = 8
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	426 elif size == 1:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	427 size = 16
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	428 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	429 size = 32
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	430 if destSize > size:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	431 needsSizeAdjust = True
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	432 prog.sizeAdjust = size
2609 fbb5115b1a27 Fix issues in CPU DSL that caused regressions in Z80 core Michael Pavone <pavone@retrodev.com> parents: 2600 diff changeset	433 else:
fbb5115b1a27 Fix issues in CPU DSL that caused regressions in Z80 core Michael Pavone <pavone@retrodev.com> parents: 2600 diff changeset	434 size = destSize
fbb5115b1a27 Fix issues in CPU DSL that caused regressions in Z80 core Michael Pavone <pavone@retrodev.com> parents: 2600 diff changeset	435 prog.lastSize = size
2463 679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	436 needsCarry = needsOflow = needsHalf = False
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	437 if op == '-':
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	438 if flagUpdates:
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	439 for flag in flagUpdates:
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	440 calc = prog.flags.flagCalc[flag]
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	441 if calc == 'carry':
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	442 needsCarry = True
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	443 elif calc == 'half-carry':
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	444 needsHalf = True
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	445 elif calc == 'overflow':
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	446 needsOflow = True
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	447 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	448 decl,name = prog.getTemp(size)
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	449 dst = prog.carryFlowDst = name
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	450 prog.lastA = 0
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	451 prog.lastB = params[0]
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	452 prog.lastBFlow = params[0]
2463 679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	453 if needsSizeAdjust:
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	454 return decl + '\n\t{dst} = {op}({a} & {mask});'.format(
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	455 dst = dst, a = params[0], op = op, mask = (1 << prog.sizeAdjust) - 1
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	456 )
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	457 if needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	458 return decl + '\n\t{dst} = ({dst} & ~{mask}) \| (({op}{a}) & {mask});'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	459 dst = dst, a = params[0], op = op, mask = (1 << prog.sizeAdjust) - 1
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	460 )
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	461 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	462 return decl + '\n\t{dst} = {op}{a};'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	463 dst = dst, a = params[0], op = op
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	464 )
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	465 self.impls['c'] = _impl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	466 self.outOp = (1,)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	467 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	468 def addImplementation(self, lang, outOp, impl):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	469 self.impls[lang] = impl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	470 if not outOp is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	471 if type(outOp) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	472 self.outOp = outOp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	473 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	474 self.outOp = (outOp,)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	475 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	476 def evaluate(self, params):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	477 return self.evalFun(*params)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	478 def canEval(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	479 return not self.evalFun is None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	480 def numArgs(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	481 return self.evalFun.__code__.co_argcount
1716 04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	482 def numParams(self):
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	483 if self.outOp:
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	484 params = max(self.outOp) + 1
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	485 else:
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	486 params = 0
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	487 if self.evalFun:
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	488 params = max(params, self.numArgs())
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	489 return params
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	490 def generate(self, otype, prog, params, rawParams, flagUpdates):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	491 if self.impls[otype].__code__.co_argcount == 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	492 return self.impls[otype](prog, params)
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	493 elif self.impls[otype].__code__.co_argcount == 3:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	494 return self.impls[otype](prog, params, rawParams)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	495 else:
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	496 return self.impls[otype](prog, params, rawParams, flagUpdates)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	497
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	498
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	499 def _xchgCImpl(prog, params, rawParams):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	500 size = prog.paramSize(rawParams[0])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	501 decl,name = prog.getTemp(size)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	502 return decl + '\n\t{tmp} = {a};\n\t{a} = {b};\n\t{b} = {tmp};'.format(a = params[0], b = params[1], tmp = name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	503
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	504 def _dispatchCImpl(prog, params):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	505 if len(params) == 1:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	506 table = 'main'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	507 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	508 table = params[1]
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	509 if prog.dispatch == 'call':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	510 return '\n\timpl_{tbl}[{op}](context, target_cycle);'.format(tbl = table, op = params[0])
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	511 elif prog.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	512 return '\n\tgoto *impl_{tbl}[{op}];'.format(tbl = table, op = params[0])
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	513 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	514 raise Exception('Unsupported dispatch type ' + prog.dispatch)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	515
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	516 def _addExplicitFlagSet(prog, output, flag, flagval):
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	517 location = prog.flags.getStorage(flag)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	518 if type(location) is tuple:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	519 reg,bit = location
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	520 reg = prog.resolveReg(reg, None, {})
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	521 value = str(1 << bit)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	522 if flagval:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	523 operator = '\|='
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	524 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	525 operator = '&='
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	526 value = '~' + value
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	527 output.append('\n\t{reg} {op} {val};'.format(reg=reg, op=operator, val=value))
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	528 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	529 reg = prog.resolveReg(location, None, {})
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	530 output.append('\n\t{reg} = {val};'.format(reg=reg, val=flagval))
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	531
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	532 def _updateFlagsCImpl(prog, params, rawParams):
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	533 autoUpdate, explicit = prog.flags.parseFlagUpdate(params[0])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	534 output = []
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	535 parity = None
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	536 directFlags = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	537 for flag in autoUpdate:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	538 calc = prog.flags.flagCalc[flag]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	539 calc,_,resultBit = calc.partition('-')
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	540 if prog.carryFlowDst:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	541 lastDst = prog.carryFlowDst
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	542 else:
1734 88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1733 diff changeset	543 lastDst = prog.resolveParam(prog.lastDst, prog.currentScope, {})
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	544 storage = prog.flags.getStorage(flag)
1705 9ab64ef5cba0 Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction Michael Pavone <pavone@retrodev.com> parents: 1704 diff changeset	545 if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half' or calc == 'overflow':
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	546 myRes = lastDst
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	547 after = ''
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	548 if calc == 'sign':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	549 resultBit = prog.getLastSize() - 1
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	550 elif calc == 'carry':
2610 2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	551 if prog.lastOp.op in ('asr', 'lsr', 'rrc', 'rlc'):
2448 d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	552 if type(prog.lastB) is int:
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	553 if prog.lastB == 0:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	554 explicit[flag] = 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	555 continue
2610 2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	556 elif prog.lastOp.op == 'rlc':
2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	557 resultBit = prog.getLastSize() - prog.lastB
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	558 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	559 resultBit = prog.lastB - 1
2448 d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions Michael Pavone <pavone@retrodev.com> parents: 2443 diff changeset	560 else:
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	561 output.append(f'\n\tif (!{prog.lastB}) {{')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	562 _addExplicitFlagSet(prog, output, flag, 0)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	563 output.append('\n\t} else {')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	564 after = '\n\t}'
2610 2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	565 if prog.lastOp.op == 'rlc':
2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	566 resultBit = f'({prog.getLastSize()} - {prog.lastB})'
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	567 else:
2610 2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	568 resultBit = f'({prog.lastB} - 1)'
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	569 myRes = prog.lastA
2610 2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	570 elif prog.lastOp.op in('rol', 'ror'):
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	571 if type(prog.lastBUnmasked) is int:
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	572 if prog.lastBUnmasked == 0:
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	573 explicit[flag] = 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	574 continue
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	575 else:
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	576 output.append(f'\n\tif (!{prog.lastBUnmasked}) {{')
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	577 _addExplicitFlagSet(prog, output, flag, 0)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	578 output.append('\n\t} else {')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	579 after = '\n\t}'
2610 2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	580 if prog.lastOp.op == 'ror':
2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	581 resultBit = prog.getLastSize() - 1
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	582 else:
2610 2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	583 resultBit = 0
2463 679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	584 elif prog.lastOp.op == 'neg':
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	585 if prog.carryFlowDst:
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	586 realSize = prog.getLastSize()
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	587 if realSize != prog.paramSize(prog.carryFlowDst):
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	588 lastDst = '({res} & {mask})'.format(res=lastDst, mask = (1 << realSize) - 1)
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	589 if type(storage) is tuple:
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	590 reg,storageBit = storage
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	591 reg = prog.resolveParam(reg, None, {})
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	592 output.append('\n\t{reg} = {res} ? ({reg} \| {bit}U) : ({reg} & {mask}U);'.format(
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	593 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	594 ))
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	595 else:
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	596 reg = prog.resolveParam(storage, None, {})
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	597 output.append('\n\t{reg} = {res} != 0;'.format(
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	598 reg = reg, res = lastDst
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	599 ))
679c31768013 Fix carry flag calculation for neg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2452 diff changeset	600 continue
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	601 else:
2610 2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	602 if prog.lastOp.op == 'lsl':
2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	603 if type(prog.lastB) is int:
2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	604 if prog.lastB == 0:
2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	605 explicit[flag] = 0
2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	606 continue
2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	607 else:
2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	608 output.append(f'\n\tif (!{prog.lastB}) {{')
2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	609 _addExplicitFlagSet(prog, output, flag, 0)
2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	610 output.append('\n\t} else {')
2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	611 after = '\n\t}'
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	612 resultBit = prog.getLastSize()
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	613 elif calc == 'half':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	614 resultBit = prog.getLastSize() - 4
1708 5bfed2eedc9d Fixed flag calculation for sub instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1707 diff changeset	615 myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst)
1705 9ab64ef5cba0 Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction Michael Pavone <pavone@retrodev.com> parents: 1704 diff changeset	616 elif calc == 'overflow':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	617 resultBit = prog.getLastSize() - 1
2621 ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	618 if prog.lastOp.op == 'lsl':
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	619 myRes = f'({prog.lastA} ^ {lastDst})'
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	620 else:
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	621 myRes = '((({a} ^ {b})) & ({a} ^ {res}))'.format(a = prog.lastA, b = prog.lastBFlow, res = lastDst)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	622 else:
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	623 #Note: offsetting this by the operation size - 8 makes sense for the Z80
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	624 #but might not for other CPUs with this kind of fixed bit flag behavior
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	625 resultBit = int(resultBit) + prog.getLastSize() - 8
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	626 if type(storage) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	627 reg,storageBit = storage
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	628 if storageBit == resultBit:
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	629 directFlags.setdefault((reg, myRes), []).append(resultBit)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	630 else:
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	631 reg = prog.resolveParam(reg, None, {})
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	632 if resultBit > storageBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	633 op = '>>'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	634 shift = resultBit - storageBit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	635 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	636 op = '<<'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	637 shift = storageBit - resultBit
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	638 output.append('\n\t{reg} = ({reg} & ~{mask}U) \| ({res} {op} {shift}U & {mask}U);'.format(
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	639 reg = reg, mask = 1 << storageBit, res = myRes, op = op, shift = shift
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	640 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	641 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	642 reg = prog.resolveParam(storage, None, {})
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	643 maxBit = prog.paramSize(storage) - 1
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	644 if type(resultBit) is int:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	645 mask = f'{1 << resultBit}U'
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	646 else:
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	647 mask = f'(1 << {resultBit})'
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	648 if not type(resultBit) is int:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	649 output.append(f'\n\t{reg} = !!({myRes} & {mask});')
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	650 elif resultBit > maxBit:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	651 mask = f'{1 << maxBit}U'
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	652 output.append('\n\t{reg} = {res} >> {shift} & {mask};'.format(reg=reg, res=myRes, shift = resultBit - maxBit, mask = mask))
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	653 else:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	654 output.append('\n\t{reg} = {res} & {mask};'.format(reg=reg, res=myRes, mask = mask))
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	655 if after:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	656 output.append(after)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	657 elif calc == 'zero':
2611 9bd90cd94000 Fix asr and lsr in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2610 diff changeset	658 realSize = prog.getLastSize()
9bd90cd94000 Fix asr and lsr in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2610 diff changeset	659 if realSize != prog.paramSize(lastDst):
9bd90cd94000 Fix asr and lsr in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2610 diff changeset	660 lastDst = '({res} & {mask})'.format(res=lastDst, mask = (1 << realSize) - 1)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	661 if type(storage) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	662 reg,storageBit = storage
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	663 reg = prog.resolveParam(reg, None, {})
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	664 output.append('\n\t{reg} = {res} ? ({reg} & {mask}U) : ({reg} \| {bit}U);'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	665 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	666 ))
1703 49a52c737bf0 Fix zero flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1702 diff changeset	667 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	668 reg = prog.resolveParam(storage, None, {})
1703 49a52c737bf0 Fix zero flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1702 diff changeset	669 output.append('\n\t{reg} = {res} == 0;'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	670 reg = reg, res = lastDst
1705 9ab64ef5cba0 Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction Michael Pavone <pavone@retrodev.com> parents: 1704 diff changeset	671 ))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	672 elif calc == 'parity':
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	673 parity = storage
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	674 paritySize = prog.getLastSize()
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	675 if prog.carryFlowDst:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	676 parityDst = paritySrc = prog.carryFlowDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	677 else:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	678 paritySrc = lastDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	679 decl,name = prog.getTemp(paritySize)
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	680 output.append(decl)
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	681 parityDst = name
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	682 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	683 raise Exception('Unknown flag calc type: ' + calc)
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	684 for reg, myRes in directFlags:
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	685 bits = directFlags[(reg, myRes)]
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	686 resolved = prog.resolveParam(reg, None, {})
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	687 if len(bits) == len(prog.flags.storageToFlags[reg]):
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	688 output.append('\n\t{reg} = {res};'.format(reg = resolved, res = myRes))
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	689 else:
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	690 mask = 0
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	691 for bit in bits:
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	692 mask \|= 1 << bit
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	693 output.append('\n\t{reg} = ({reg} & ~{mask}U) \| ({res} & {mask}U);'.format(
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	694 reg = resolved, mask = mask, res = myRes
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	695 ))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	696 if prog.carryFlowDst:
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	697 if prog.lastOp.op != 'cmp':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	698 if prog.sizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	699 output.append('\n\t{dst} = ({dst} & ~{mask}) \| ({tmpdst} & {mask});'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	700 dst = prog.resolveParam(prog.lastDst, prog.currentScope, {}), tmpdst = prog.carryFlowDst, mask = ((1 << prog.sizeAdjust) - 1)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	701 ))
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	702 prog.sizeAdjust = None
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	703 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	704 output.append('\n\t{dst} = {tmpdst};'.format(dst = prog.resolveParam(prog.lastDst, prog.currentScope, {}), tmpdst = prog.carryFlowDst))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	705 prog.carryFlowDst = None
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	706 if parity:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	707 if paritySize > 8:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	708 if paritySize > 16:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	709 output.append('\n\t{dst} = {src} ^ ({src} >> 16);'.format(dst=parityDst, src=paritySrc))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	710 paritySrc = parityDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	711 output.append('\n\t{dst} = {src} ^ ({src} >> 8);'.format(dst=parityDst, src=paritySrc))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	712 paritySrc = parityDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	713 output.append('\n\t{dst} = ({src} ^ ({src} >> 4)) & 0xF;'.format(dst=parityDst, src=paritySrc))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	714 if type(parity) is tuple:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	715 reg,bit = parity
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	716 reg = prog.resolveParam(reg, None, {})
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	717 output.append('\n\t{flag} = ({flag} & ~{mask}U) \| ((0x6996 >> {parity}) << {bit} & {mask}U);'.format(
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	718 flag=reg, mask = 1 << bit, bit = bit, parity = parityDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	719 ))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	720 else:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	721 reg = prog.resolveParam(parity, None, {})
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	722 output.append('\n\t{flag} = 0x9669 >> {parity} & 1;'.format(flag=reg, parity=parityDst))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	723
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	724 #TODO: combine explicit flags targeting the same storage location
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	725 for flag in explicit:
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	726 _addExplicitFlagSet(prog, output, flag, explicit[flag])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	727 return ''.join(output)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	728
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	729 def _cmpCImpl(prog, params, rawParams, flagUpdates):
2451 edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	730 b_size = size = prog.paramSize(rawParams[1])
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	731 needsCarry = False
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	732 if flagUpdates:
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	733 for flag in flagUpdates:
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	734 calc = prog.flags.flagCalc[flag]
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	735 if calc == 'carry':
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	736 needsCarry = True
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	737 break
2451 edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	738 if len(params) > 2:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	739 size = params[2]
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	740 if size == 0:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	741 size = 8
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	742 elif size == 1:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	743 size = 16
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	744 else:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	745 size = 32
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	746 prog.lastSize = size
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	747 if needsCarry:
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	748 size *= 2
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	749 tmpvar = 'cmp_tmp{sz}__'.format(sz=size)
1745 a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	750 if flagUpdates:
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	751 prog.carryFlowDst = tmpvar
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	752 prog.lastA = params[1]
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	753 prog.lastB = params[0]
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	754 prog.lastBFlow = params[0]
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	755 scope = prog.getRootScope()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	756 if not scope.resolveLocal(tmpvar):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	757 scope.addLocal(tmpvar, size)
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	758 prog.lastDst = rawParams[1]
2451 edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	759 a = params[0]
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	760 b = params[1]
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	761 a_size = prog.paramSize(rawParams[0])
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	762 if prog.lastSize != a_size:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	763 a = '(({a}) & {mask})'.format(a = a, mask = (1 << prog.lastSize) - 1)
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	764 if prog.lastSize != b_size:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	765 b = '(({b}) & {mask})'.format(b = b, mask = (1 << prog.lastSize) - 1)
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	766 if size == 64:
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	767 a = '((uint64_t){a})'.format(a = a)
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	768 b = '((uint64_t){b})'.format(b = b)
edd73a009537 Fix implementation of cmp for 32-bit operands or when operation size is smaller than the size of the operands Michael Pavone <pavone@retrodev.com> parents: 2448 diff changeset	769 return '\n\t{var} = {b} - {a};'.format(var = tmpvar, a = a, b = b)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	770
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	771 def _asrCImpl(prog, params, rawParams, flagUpdates):
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	772 needsCarry = False
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	773 if flagUpdates:
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	774 for flag in flagUpdates:
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	775 calc = prog.flags.flagCalc[flag]
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	776 if calc == 'carry':
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	777 needsCarry = True
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	778 decl = ''
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	779 needsSizeAdjust = False
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	780 destSize = prog.paramSize(rawParams[2])
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	781 if len(params) > 3:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	782 size = params[3]
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	783 if size == 0:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	784 size = 8
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	785 elif size == 1:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	786 size = 16
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	787 else:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	788 size = 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	789 if destSize > size:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	790 needsSizeAdjust = True
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	791 prog.sizeAdjust = size
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	792 else:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	793 size = destSize
2609 fbb5115b1a27 Fix issues in CPU DSL that caused regressions in Z80 core Michael Pavone <pavone@retrodev.com> parents: 2600 diff changeset	794 prog.lastSize = size
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	795 mask = 1 << (size - 1)
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	796 if needsCarry:
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	797 decl,name = prog.getTemp(size)
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	798 dst = prog.carryFlowDst = name
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	799 prog.lastA = params[0]
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	800 prog.lastB = params[1]
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	801 if needsSizeAdjust:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	802 sizeMask = (1 << size) - 1
2611 9bd90cd94000 Fix asr and lsr in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2610 diff changeset	803 return decl + '\n\t{name} = (({a} & {sizeMask}) >> ({b} & {sizeMask})) \| (({a} & {mask}) && {b} ? 0xFFFFFFFFU << ({size} - ({b} & {sizeMask})) : 0);'.format(
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	804 name = name, a = params[0], b = params[1], dst = dst, mask = mask, size=size, sizeMask=sizeMask)
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	805 elif needsSizeAdjust:
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	806 decl,name = prog.getTemp(size)
ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	807 sizeMask = (1 << size) - 1
2611 9bd90cd94000 Fix asr and lsr in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2610 diff changeset	808 return decl + ('\n\t{name} = (({a} & {sizeMask}) >> ({b} & {sizeMask})) \| (({a} & {mask}) && {b} ? 0xFFFFFFFFU << ({size} - ({b} & {sizeMask})) : 0);' +
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	809 '\n\t{dst} = ({dst} & ~{sizeMask}) \| {name};').format(
2611 9bd90cd94000 Fix asr and lsr in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2610 diff changeset	810 name = name, a = params[0], b = params[1], dst = params[2], mask = mask, size=size, sizeMask=sizeMask)
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	811 else:
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	812 dst = params[2]
2502 ad50530a7c27 Partially functional asr/asl implementations in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	813
2611 9bd90cd94000 Fix asr and lsr in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2610 diff changeset	814 return decl + '\n\t{dst} = ({a} >> {b}) \| (({a} & {mask}) && {b} ? 0xFFFFFFFFU << ({size} - {b}) : 0);'.format(
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	815 a = params[0], b = params[1], dst = dst, mask = mask, size=size)
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	816
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	817 def _sext(size, src):
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	818 if size == 16:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	819 return src \| 0xFF00 if src & 0x80 else src & 0x7F
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	820 else:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	821 return src \| 0xFFFF0000 if src & 0x8000 else src & 0x7FFF
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	822
2598 8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	823 def _sextCImpl(prog, params, rawParams):
8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	824 if not type(params[0]) is int:
8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	825 raise Exception('First param to sext must resolve to an integer')
8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	826 if not params[0] in (16, 32):
8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	827 raise Exception('First param to sext must be 16 or 32')
8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	828 fromSize = params[0] >> 1
8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	829 srcMask = (1 << fromSize) - 1
8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	830 dstMask = (1 << params[0]) - 1
8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	831 if prog.paramSize(rawParams[1]) > fromSize:
8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	832 if type(params[1]) is int:
8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	833 src = params[1] & srcMask
8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	834 else:
8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	835 src = f'({params[1]} & {srcMask})'
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	836 else:
2598 8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	837 src = params[1]
8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	838 signBit = 1 << (fromSize - 1)
8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	839 extend = (0xFFFFFFFF << fromSize) & dstMask
2468 0ca78837e4d2 Implement ext instruction in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2463 diff changeset	840 prog.lastSize = params[0]
2598 8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	841 if prog.paramSize(rawParams[2]) > params[0]:
8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	842 return f'\n\t{params[2]} = ({params[2]} & ~{dstMask}) \| ({src} & {signBit} ? {src} \| {extend} : {src});'
8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	843 else:
8fd2dbe34883 Fix masking issues in CPU DSL sext instruction Michael Pavone <pavone@retrodev.com> parents: 2597 diff changeset	844 return f'\n\t{params[2]} = {src} & {signBit} ? {src} \| {extend} : {src};'
2562 595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	845
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	846 def _mulsCImpl(prog, params, rawParams, flagUpdates):
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	847 p0Size = prog.paramSize(rawParams[0])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	848 p1Size = prog.paramSize(rawParams[1])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	849 destSize = prog.paramSize(rawParams[2])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	850 if len(params) > 3:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	851 size = params[3]
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	852 if size == 0:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	853 size = 8
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	854 elif size == 1:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	855 size = 16
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	856 else:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	857 size = 32
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	858 else:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	859 size = destSize
2637 47e197d40ffe Fix flags for mulu/muls in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2621 diff changeset	860 prog.lastSize = size
2562 595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	861 if p0Size >= size:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	862 p0Size = size // 2
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	863 if p1Size >= size:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	864 p1Size = size // 2
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	865 #TODO: Handle case in which destSize > size
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	866 return f'\n\t{params[2]} = (int{size}_t)(((int{p0Size}_t){params[0]}) * ((int{p1Size}_t){params[1]}));'
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	867
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	868 def _muluCImpl(prog, params, rawParams, flagUpdates):
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	869 p0Size = prog.paramSize(rawParams[0])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	870 p1Size = prog.paramSize(rawParams[1])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	871 destSize = prog.paramSize(rawParams[2])
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	872 if len(params) > 3:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	873 size = params[3]
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	874 if size == 0:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	875 size = 8
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	876 elif size == 1:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	877 size = 16
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	878 else:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	879 size = 32
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	880 else:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	881 size = destSize
2637 47e197d40ffe Fix flags for mulu/muls in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2621 diff changeset	882 prog.lastSize = size
2562 595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	883 if p0Size >= size:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	884 p0Size = size // 2
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	885 if p1Size >= size:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	886 p1Size = size // 2
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	887 #TODO: Handle case in which destSize > size
2672 6894a25ebfaa Fix mulu nflag when compiling with optimization enabled Michael Pavone <pavone@retrodev.com> parents: 2666 diff changeset	888 p0Mask = (1 << p0Size) - 1
6894a25ebfaa Fix mulu nflag when compiling with optimization enabled Michael Pavone <pavone@retrodev.com> parents: 2666 diff changeset	889 p1Mask = (1 << p1Size) - 1
6894a25ebfaa Fix mulu nflag when compiling with optimization enabled Michael Pavone <pavone@retrodev.com> parents: 2666 diff changeset	890 return f'\n\t{params[2]} = ((uint{size}_t)({params[0]} & {p0Mask})) * ((uint{size}_t)({params[1]} & {p1Mask}));'
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	891
73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	892 def _getCarryCheck(prog):
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	893 carryFlag = None
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	894 for flag in prog.flags.flagOrder:
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	895 if prog.flags.flagCalc[flag] == 'carry':
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	896 carryFlag = flag
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	897 break
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	898 if carryFlag is None:
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	899 raise Exception('adc requires a defined carry flag')
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	900 carryStorage = prog.flags.getStorage(carryFlag)
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	901 if type(carryStorage) is tuple:
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	902 reg,bit = carryStorage
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	903 reg = prog.resolveReg(reg, None, (), False)
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	904 return '({reg} & 1 << {bit})'.format(reg=reg, bit=bit)
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	905 else:
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	906 return prog.resolveReg(carryStorage, None, (), False)
73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	907
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	908 def _adcCImpl(prog, params, rawParams, flagUpdates):
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	909 needsSizeAdjust = False
2599 ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	910 destSize = prog.paramSize(rawParams[2])
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	911 if len(params) > 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	912 size = params[3]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	913 if size == 0:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	914 size = 8
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	915 elif size == 1:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	916 size = 16
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	917 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	918 size = 32
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	919 if destSize > size:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	920 needsSizeAdjust = True
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	921 prog.sizeAdjust = size
2599 ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	922 else:
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	923 size = destSize
2609 fbb5115b1a27 Fix issues in CPU DSL that caused regressions in Z80 core Michael Pavone <pavone@retrodev.com> parents: 2600 diff changeset	924 prog.lastSize = size
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	925 needsCarry = needsOflow = needsHalf = False
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	926 if flagUpdates:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	927 for flag in flagUpdates:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	928 calc = prog.flags.flagCalc[flag]
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	929 if calc == 'carry':
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	930 needsCarry = True
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	931 elif calc == 'half-carry':
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	932 needsHalf = True
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	933 elif calc == 'overflow':
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	934 needsOflow = True
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	935 decl = ''
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	936 carryCheck = _getCarryCheck(prog)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	937 vals = '1 : 0'
2599 ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	938 mask = (1 << size) - 1
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	939 if prog.paramSize(rawParams[0]) > size:
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	940 if type(params[0]) is int:
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	941 a = params[0] & mask
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	942 else:
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	943 a = f'({params[0]} & {mask})'
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	944 else:
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	945 a = params[0]
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	946 if prog.paramSize(rawParams[1]) > size:
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	947 if type(params[1]) is int:
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	948 b = params[1] & mask
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	949 else:
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	950 b = f'({params[1]} & {mask})'
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	951 else:
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	952 b = params[1]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	953 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	954 if needsCarry:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	955 size *= 2
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	956 decl,name = prog.getTemp(size)
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	957 dst = prog.carryFlowDst = name
2599 ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	958 prog.lastA = a
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	959 prog.lastB = b
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	960 prog.lastBFlow = f'(~{b})'
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	961 if size == 64:
2599 ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	962 a = f'((uint64_t){a})'
ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	963 b = f'((uint64_t){b})'
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	964 vals = '((uint64_t)1) : ((uint64_t)0)'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	965 elif needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	966 decl,name = prog.getTemp(size)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	967 dst = params[2]
2599 ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	968 return f'{decl}\n\t{tmp} = {a} + {b} + ({carryCheck} ? 1 : 0);\n\t{dst} = ({dst} & ~{mask}) \| {tmp};'
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	969 else:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	970 dst = params[2]
2599 ca8141c2d6ba Fix masking issue in CPU DSL adc fixing issues in 68K core addx and abcd Michael Pavone <pavone@retrodev.com> parents: 2598 diff changeset	971 return decl + f'\n\t{dst} = {a} + {b} + ({carryCheck} ? {vals});'
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	972
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	973 def _sbcCImpl(prog, params, rawParams, flagUpdates):
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	974 needsSizeAdjust = False
2597 142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	975 destSize = prog.paramSize(rawParams[2])
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	976 if len(params) > 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	977 size = params[3]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	978 if size == 0:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	979 size = 8
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	980 elif size == 1:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	981 size = 16
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	982 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	983 size = 32
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	984 if destSize > size:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	985 needsSizeAdjust = True
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	986 prog.sizeAdjust = size
2597 142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	987 else:
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	988 size = destSize
2609 fbb5115b1a27 Fix issues in CPU DSL that caused regressions in Z80 core Michael Pavone <pavone@retrodev.com> parents: 2600 diff changeset	989 prog.lastSize = size
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	990 needsCarry = needsOflow = needsHalf = False
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	991 if flagUpdates:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	992 for flag in flagUpdates:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	993 calc = prog.flags.flagCalc[flag]
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	994 if calc == 'carry':
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	995 needsCarry = True
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	996 elif calc == 'half-carry':
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	997 needsHalf = True
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	998 elif calc == 'overflow':
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	999 needsOflow = True
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	1000 decl = ''
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	1001 carryCheck = _getCarryCheck(prog)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1002 vals = '1 : 0'
2597 142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1003 mask = (1 << size) - 1
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1004 if prog.paramSize(rawParams[0]) > size:
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1005 if type(params[0]) is int:
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1006 b = params[0] & mask
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1007 else:
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1008 b = f'({params[0]} & {mask})'
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1009 else:
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1010 b = params[0]
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1011 if prog.paramSize(rawParams[1]) > size:
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1012 if type(params[1]) is int:
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1013 a = params[1] & mask
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1014 else:
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1015 a = f'({params[1]} & {mask})'
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1016 else:
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1017 a = params[1]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1018 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	1019 if needsCarry:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	1020 size *= 2
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	1021 decl,name = prog.getTemp(size)
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	1022 dst = prog.carryFlowDst = name
2597 142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1023 prog.lastA = a
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1024 prog.lastB = b
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1025 prog.lastBFlow = b
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1026 if size == 64:
2597 142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1027 a = f'((uint64_t){a})'
142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1028 b = f'((uint64_t){b})'
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1029 vals = '((uint64_t)1) : ((uint64_t)0)'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1030 elif needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1031 decl,name = prog.getTemp(size)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1032 dst = params[2]
2597 142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1033 return f'{decl}\n\t{name} = {a} - {b} - ({carryCheck} ? 1 : 0);\n\t{dst} = ({dst} & ~{mask}) \| {tmp};'
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	1034 else:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	1035 dst = params[2]
2597 142bb1eb8ab2 Fix bug in sbc in CPU DSL impacting 68K subx and sbcd Michael Pavone <pavone@retrodev.com> parents: 2594 diff changeset	1036 return decl + f'\n\t{dst} = {a} - {b} - ({_getCarryCheck(prog)} ? {vals});'
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1037
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1038 def _rolCImpl(prog, params, rawParams, flagUpdates):
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1039 needsCarry = False
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1040 if flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1041 for flag in flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1042 calc = prog.flags.flagCalc[flag]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1043 if calc == 'carry':
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1044 needsCarry = True
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1045 destSize = prog.paramSize(rawParams[2])
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1046 needsSizeAdjust = False
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1047 if len(params) > 3:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1048 size = params[3]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1049 if size == 0:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1050 size = 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1051 elif size == 1:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1052 size = 16
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1053 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1054 size = 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1055 if destSize > size:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1056 needsSizeAdjust = True
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1057 if needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1058 prog.sizeAdjust = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1059 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1060 size = destSize
2609 fbb5115b1a27 Fix issues in CPU DSL that caused regressions in Z80 core Michael Pavone <pavone@retrodev.com> parents: 2600 diff changeset	1061 prog.lastSize = size
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1062 rotMask = size - 1
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1063 if type(params[1]) is int:
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1064 b = params[1] & rotMask
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1065 mdecl = ''
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1066 ret = ''
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1067 else:
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1068 mdecl,b = prog.getTemp(prog.paramSize(rawParams[1]))
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1069 ret = f'\n\t{b} = {params[1]} & {rotMask};'
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1070 prog.lastB = b
2594 1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1071 if prog.paramSize(rawParams[0]) > size:
1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1072 mask = (1 << size) - 1
1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1073 a = f'({params[0]} & {mask})'
1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1074 else:
1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1075 a = params[0]
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1076 prog.lastBUnmasked = params[1]
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1077 if needsSizeAdjust:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1078 decl,name = prog.getTemp(size)
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1079 mdecl += decl
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1080 dst = prog.carryFlowDst = name
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1081 else:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1082 dst = params[2]
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1083 ret += '\n\t{dst} = {a} << {b} \| {a} >> ({size} - {b});'.format(dst = dst,
2594 1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1084 a = a, b = b, size=size
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1085 )
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1086 if needsSizeAdjust and not needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1087 mask = (1 << size) - 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1088 ret += f'\n\t{params[2]} = ({params[2]} & ~{mask}) \| ({dst} & {mask});'
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1089 return mdecl + ret
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1090
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1091 def _rlcCImpl(prog, params, rawParams, flagUpdates):
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1092 needsCarry = False
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1093 if flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1094 for flag in flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1095 calc = prog.flags.flagCalc[flag]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1096 if calc == 'carry':
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1097 needsCarry = True
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1098 decl = ''
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1099 destSize = prog.paramSize(rawParams[2])
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1100 needsSizeAdjust = False
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1101 if len(params) > 3:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1102 size = params[3]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1103 if size == 0:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1104 size = 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1105 elif size == 1:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1106 size = 16
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1107 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1108 size = 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1109 if destSize > size:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1110 needsSizeAdjust = True
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1111 if needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1112 prog.sizeAdjust = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1113 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1114 size = destSize
2609 fbb5115b1a27 Fix issues in CPU DSL that caused regressions in Z80 core Michael Pavone <pavone@retrodev.com> parents: 2600 diff changeset	1115 prog.lastSize = size
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1116 carryCheck = _getCarryCheck(prog)
2594 1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1117 if prog.paramSize(rawParams[0]) > size:
1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1118 mask = (1 << size) - 1
1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1119 a = f'({params[0]} & {mask})'
1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1120 else:
1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1121 a = params[0]
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1122 if needsCarry or needsSizeAdjust:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1123 decl,name = prog.getTemp(size)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1124 dst = prog.carryFlowDst = name
2594 1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1125 prog.lastA = a
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1126 prog.lastB = params[1]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1127 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1128 dst = params[2]
2594 1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1129 if size == 32 and ((not type(params[1]) is int) or params[1] <= 1):
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1130 # we may need to shift by 32-bits which is too much for a normal int
2594 1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1131 a = f'((uint64_t){a})'
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1132 ret = decl + '\n\t{dst} = {a} << {b} \| {a} >> ({size} + 1 - {b}) \| ({check} ? 1 : 0) << ({b} - 1);'.format(dst = dst,
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1133 a = a, b = params[1], size=size, check=carryCheck
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1134 )
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1135 if needsSizeAdjust and not needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1136 mask = (1 << size) - 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1137 ret += f'\n\t{params[2]} = ({params[2]} & ~{mask}) \| ({dst} & {mask});'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1138 return ret
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1139
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1140 def _rorCImpl(prog, params, rawParams, flagUpdates):
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1141 needsCarry = False
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1142 if flagUpdates:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1143 for flag in flagUpdates:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1144 calc = prog.flags.flagCalc[flag]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1145 if calc == 'carry':
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1146 needsCarry = True
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1147 destSize = prog.paramSize(rawParams[2])
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1148 needsSizeAdjust = False
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1149 if len(params) > 3:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1150 size = params[3]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1151 if size == 0:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1152 size = 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1153 elif size == 1:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1154 size = 16
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1155 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1156 size = 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1157 if destSize > size:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1158 needsSizeAdjust = True
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1159 if needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1160 prog.sizeAdjust = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1161 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1162 size = destSize
2609 fbb5115b1a27 Fix issues in CPU DSL that caused regressions in Z80 core Michael Pavone <pavone@retrodev.com> parents: 2600 diff changeset	1163 prog.lastSize = size
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1164 rotMask = size - 1
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1165 if type(params[1]) is int:
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1166 b = params[1] & rotMask
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1167 mdecl = ''
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1168 ret = ''
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1169 else:
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1170 mdecl,b = prog.getTemp(prog.paramSize(rawParams[1]))
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1171 ret = f'\n\t{b} = {params[1]} & {rotMask};'
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1172 prog.lastB = b
9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1173 prog.lastBUnmasked = params[1]
2594 1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1174 if prog.paramSize(rawParams[0]) > size:
1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1175 mask = (1 << size) - 1
1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1176 a = f'({params[0]} & {mask})'
1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1177 else:
1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1178 a = params[0]
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1179 if needsSizeAdjust:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1180 decl,name = prog.getTemp(size)
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1181 dst = prog.carryFlowDst = name
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1182 mdecl += decl
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1183 else:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1184 dst = params[2]
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1185 ret += '\n\t{dst} = {a} >> {b} \| {a} << ({size} - {b});'.format(dst = dst,
2594 1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1186 a = a, b = b, size=size
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1187 )
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1188 if needsSizeAdjust and not needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1189 mask = (1 << size) - 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1190 ret += f'\n\t{params[2]} = ({params[2]} & ~{mask}) \| ({dst} & {mask});'
2578 9b01541cbd60 Fix rol and ror in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2577 diff changeset	1191 return mdecl + ret
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1192
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1193 def _rrcCImpl(prog, params, rawParams, flagUpdates):
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1194 needsCarry = False
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1195 if flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1196 for flag in flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1197 calc = prog.flags.flagCalc[flag]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1198 if calc == 'carry':
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1199 needsCarry = True
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1200 decl = ''
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1201 destSize = prog.paramSize(rawParams[2])
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1202 needsSizeAdjust = False
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1203 if len(params) > 3:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1204 size = params[3]
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1205 if size == 0:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1206 size = 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1207 elif size == 1:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1208 size = 16
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1209 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1210 size = 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1211 if destSize > size:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1212 needsSizeAdjust = True
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1213 if needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1214 prog.sizeAdjust = size
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1215 else:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1216 size = destSize
2609 fbb5115b1a27 Fix issues in CPU DSL that caused regressions in Z80 core Michael Pavone <pavone@retrodev.com> parents: 2600 diff changeset	1217 prog.lastSize = size
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1218 carryCheck = _getCarryCheck(prog)
2594 1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1219 if prog.paramSize(rawParams[0]) > size:
1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1220 mask = (1 << size) - 1
1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1221 a = f'({params[0]} & {mask})'
1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1222 else:
1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1223 a = params[0]
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1224 if needsCarry or needsSizeAdjust:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1225 decl,name = prog.getTemp(size)
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1226 dst = prog.carryFlowDst = name
2594 1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1227 prog.lastA = a
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1228 prog.lastB = params[1]
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1229 else:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1230 dst = params[2]
2594 1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1231 if size == 32 and ((not type(params[1]) is int) or params[1] <= 1):
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1232 # we may need to shift by 32-bits which is too much for a normal int
2594 1c493b8c513b Fix some rotate instruction issues in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2592 diff changeset	1233 a = f'((uint64_t){a})'
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1234 ret = decl + '\n\t{dst} = {a} >> {b} \| {a} << ({size} + 1 - {b}) \| ({check} ? 1 : 0) << ({size}-{b});'.format(dst = dst,
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1235 a = a, b = params[1], size=size, check=carryCheck
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1236 )
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1237 if needsSizeAdjust and not needsCarry:
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1238 mask = (1 << size) - 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1239 ret += f'\n\t{params[2]} = ({params[2]} & ~{mask}) \| ({dst} & {mask});'
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	1240 return ret
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1241
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1242 def _updateSyncCImpl(prog, params):
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	1243 return '\n\t{sync}(context, target_cycle);'.format(sync=prog.sync_cycle)
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	1244
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1245 _opMap = {
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1246 'mov': Op(lambda val: val).cUnaryOperator(''),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1247 'not': Op(lambda val: ~val).cUnaryOperator('~'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1248 'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1249 'neg': Op(lambda val: -val).cUnaryOperator('-'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1250 'add': Op(lambda a, b: a + b).cBinaryOperator('+'),
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	1251 'adc': Op().addImplementation('c', 2, _adcCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1252 'sub': Op(lambda a, b: b - a).cBinaryOperator('-'),
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	1253 'sbc': Op().addImplementation('c', 2, _sbcCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1254 'lsl': Op(lambda a, b: a << b).cBinaryOperator('<<'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1255 'lsr': Op(lambda a, b: a >> b).cBinaryOperator('>>'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1256 'asr': Op(lambda a, b: a >> b).addImplementation('c', 2, _asrCImpl),
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1257 'rol': Op().addImplementation('c', 2, _rolCImpl),
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1258 'rlc': Op().addImplementation('c', 2, _rlcCImpl),
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1259 'ror': Op().addImplementation('c', 2, _rorCImpl),
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1260 'rrc': Op().addImplementation('c', 2, _rrcCImpl),
2562 595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1261 'mulu': Op(lambda a, b: a * b).addImplementation('c', 2, _muluCImpl),
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1262 'muls': Op().addImplementation('c', 2, _mulsCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1263 'and': Op(lambda a, b: a & b).cBinaryOperator('&'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1264 'or': Op(lambda a, b: a \| b).cBinaryOperator('\|'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1265 'xor': Op(lambda a, b: a ^ b).cBinaryOperator('^'),
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1266 'abs': Op(lambda val: abs(val)).addImplementation(
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1267 'c', 1, lambda prog, params: '\n\t{dst} = abs({src});'.format(dst=params[1], src=params[0])
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1268 ),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1269 'cmp': Op().addImplementation('c', None, _cmpCImpl),
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	1270 'sext': Op(_sext).addImplementation('c', 2, _sextCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1271 'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1272 pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]])
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	1273 )),
2587 e04c7e753bf6 Implement divs and divu in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2581 diff changeset	1274 'ccall': Op().addImplementation('c', None, lambda prog, params: '\n\t{fun}({args});'.format(
e04c7e753bf6 Implement divs and divu in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2581 diff changeset	1275 pre = prog.prefix, fun = params[0], args = ', '.join([str(p) for p in params[1:]])
e04c7e753bf6 Implement divs and divu in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2581 diff changeset	1276 )),
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1277 'pcall': Op().addImplementation('c', None, lambda prog, params: '\n\t(({typ}){fun})({args});'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1278 typ = params[1], fun = params[0], args = ', '.join([str(p) for p in params[2:]])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1279 )),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1280 'cycles': Op().addImplementation('c', None,
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1281 lambda prog, params: '\n\tcontext->cycles += context->opts->gen.clock_divider * {0};'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1282 params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1283 )
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1284 ),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1285 'addsize': Op(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1286 lambda a, b: b + (2 * a if a else 1)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1287 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} + ({sz} ? {sz} * 2 : 1);'.format(
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1288 dst = params[2], sz = params[0], val = params[1]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1289 )),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1290 'decsize': Op(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1291 lambda a, b: b - (2 * a if a else 1)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1292 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} - ({sz} ? {sz} * 2 : 1);'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1293 dst = params[2], sz = params[0], val = params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1294 )),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1295 'xchg': Op().addImplementation('c', (0,1), _xchgCImpl),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1296 'dispatch': Op().addImplementation('c', None, _dispatchCImpl),
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1297 'update_flags': Op().addImplementation('c', None, _updateFlagsCImpl),
2618 1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1298 'update_sync': Op().addImplementation('c', None, _updateSyncCImpl),
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1299 'break': Op().addImplementation('c', None, lambda prog, params: '\n\tbreak;')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1300 }
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1301
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1302 #represents a simple DSL instruction
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1303 class NormalOp:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1304 def __init__(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1305 self.op = parts[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1306 self.params = parts[1:]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1307
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1308 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1309 procParams = []
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1310 allParamsConst = flagUpdates is None and not prog.conditional
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1311 opDef = _opMap.get(self.op)
2615 cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1312 if self.op == 'xchg':
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1313 #xchg uses its regs as both source and destination
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1314 #we need to resolve as both so that disperse/coalesce flag stuff gets done
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1315 #it also interacts weirdly with constant folding
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1316 a = prog.resolveParam(self.params[0], parent, fieldVals, True, False)
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1317 b = prog.resolveParam(self.params[1], parent, fieldVals, True, False)
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1318 dsta = prog.resolveParam(self.params[0], parent, fieldVals, False, True)
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1319 dstb = prog.resolveParam(self.params[1], parent, fieldVals, False, True)
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1320 dsta_nocontext = dsta[len("context->"):] if dsta.startswith('context->') else dsta
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1321 dstb_nocontext = dstb[len("context->"):] if dstb.startswith('context->') else dstb
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1322 if type(a) is int:
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1323 if type(b) is int:
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1324 #both params are constant, fold
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1325 parent.regValues[dsta_nocontext] = b
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1326 parent.regValues[dstb_nocontext] = a
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1327 if prog.isReg(dsta_nocontext):
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1328 output.append(_opMap['mov'].generate(otype, prog, (b, dsta), (self.params[1], self.params[0]), None))
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1329 if prog.isReg(dstb_nocontext):
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1330 output.append(_opMap['mov'].generate(otype, prog, (a, dstb), (self.params[0], self.params[1]), None))
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1331 else:
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1332 parent.regValues[dstb_nocontext] = a
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1333 del parent.regValues[dsta_nocontext]
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1334 output.append(_opMap['mov'].generate(otype, prog, (b, dsta), (self.params[1], self.params[0]), None))
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1335 if prog.isReg(dstb_nocontext):
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1336 output.append(_opMap['mov'].generate(otype, prog, (a, dstb), (self.params[0], self.params[1]), None))
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1337 prog.lastOp = self
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1338 return
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1339 elif type(b) is int:
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1340 parent.regValues[dsta_nocontext] = b
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1341 del parent.regValues[dstb_nocontext]
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1342 output.append(_opMap['mov'].generate(otype, prog, (a, dstb), (self.params[0], self.params[1]), None))
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1343 if prog.isReg(dsta_nocontext):
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1344 output.append(_opMap['mov'].generate(otype, prog, (b, dsta), (self.params[1], self.params[0]), None))
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1345 prog.lastOp = self
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1346 return
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1347 else:
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1348 procParams = [dsta, dstb]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1349 allParamsConst = False
2615 cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1350 else:
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1351 for param in self.params:
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1352 isDst = (not opDef is None) and len(procParams) in opDef.outOp
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1353 allowConst = (self.op in prog.subroutines or not isDst) and param in parent.regValues
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1354 param = prog.resolveParam(param, parent, fieldVals, allowConst, isDst)
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1355
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1356 if (not type(param) is int) and len(procParams) != len(self.params) - 1:
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1357 allParamsConst = False
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1358 procParams.append(param)
2587 e04c7e753bf6 Implement divs and divu in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2581 diff changeset	1359 if prog.needFlagCoalesce:
e04c7e753bf6 Implement divs and divu in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2581 diff changeset	1360 output.append(prog.flags.coalesceFlags(prog, otype))
e04c7e753bf6 Implement divs and divu in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2581 diff changeset	1361 prog.needFlagCoalesce = False
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1362
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1363 if self.op == 'meta':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1364 param,_,index = self.params[1].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1365 if index:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1366 index = (parent.resolveLocal(index) or index)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1367 if index in fieldVals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1368 index = str(fieldVals[index])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1369 param = param + '.' + index
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1370 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1371 param = parent.resolveLocal(param) or param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1372 if param in fieldVals:
1991 7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core Michael Pavone <pavone@retrodev.com> parents: 1938 diff changeset	1373 param = fieldVals[param]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1374 prog.meta[self.params[0]] = param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1375 elif self.op == 'dis':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1376 #TODO: Disassembler
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1377 pass
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1378 elif not opDef is None:
1716 04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1379 if opDef.numParams() > len(procParams):
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	1380 raise Exception('Insufficient params for ' + self.op + ' (' + ', '.join(self.params) + ')')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1381 if opDef.canEval() and allParamsConst:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1382 #do constant folding
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1383 if opDef.numArgs() >= len(procParams):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1384 raise Exception('Insufficient args for ' + self.op + ' (' + ', '.join(self.params) + ')')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1385 dst = self.params[opDef.numArgs()]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1386 result = opDef.evaluate(procParams[:opDef.numArgs()])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1387 while dst in prog.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1388 dst = prog.meta[dst]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1389 maybeLocal = parent.resolveLocal(dst)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1390 if maybeLocal:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1391 dst = maybeLocal
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1392 parent.regValues[dst] = result
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1393 if prog.isReg(dst):
2497 95d9809a3973 Fix constant propagation for sext instruction Michael Pavone <pavone@retrodev.com> parents: 2478 diff changeset	1394 shortProc = (result, procParams[-1])
95d9809a3973 Fix constant propagation for sext instruction Michael Pavone <pavone@retrodev.com> parents: 2478 diff changeset	1395 shortParams = (result, self.params[-1])
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1396 output.append(_opMap['mov'].generate(otype, prog, shortProc, shortParams, None))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1397 else:
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1398 output.append(opDef.generate(otype, prog, procParams, self.params, flagUpdates))
1728 b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1399 for dstIdx in opDef.outOp:
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1400 dst = self.params[dstIdx]
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1401 while dst in prog.meta:
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1402 dst = prog.meta[dst]
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1403 if dst in parent.regValues:
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	1404 del parent.regValues[dst]
2615 cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1405 if self.op in ('ocall', 'ccall', 'pcall'):
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1406 #we called in to arbitrary C code, assume any reg could have changed
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1407 to_clear = []
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1408 for name in parent.regValues:
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1409 if prog.isReg(name):
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1410 to_clear.append(name)
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1411 for name in to_clear:
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	1412 del parent.regValues[name]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1413 elif self.op in prog.subroutines:
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1414 procParams = []
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1415 for param in self.params:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1416 begin,sep,end = param.partition('.')
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1417 if sep:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1418 if end in fieldVals:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1419 param = begin + '.' + str(fieldVals[end])
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1420 else:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1421 if param in fieldVals:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1422 param = fieldVals[param]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1423 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1424 maybeLocal = parent.resolveLocal(param)
2704 c5dce4284e69 Fix a couple of bugs in CPU DSL found while working on uPD78K/II core Michael Pavone <pavone@retrodev.com> parents: 2680 diff changeset	1425 if maybeLocal:
c5dce4284e69 Fix a couple of bugs in CPU DSL found while working on uPD78K/II core Michael Pavone <pavone@retrodev.com> parents: 2680 diff changeset	1426 if maybeLocal in parent.regValues:
c5dce4284e69 Fix a couple of bugs in CPU DSL found while working on uPD78K/II core Michael Pavone <pavone@retrodev.com> parents: 2680 diff changeset	1427 param = parent.regValues[maybeLocal]
c5dce4284e69 Fix a couple of bugs in CPU DSL found while working on uPD78K/II core Michael Pavone <pavone@retrodev.com> parents: 2680 diff changeset	1428 else:
c5dce4284e69 Fix a couple of bugs in CPU DSL found while working on uPD78K/II core Michael Pavone <pavone@retrodev.com> parents: 2680 diff changeset	1429 param = maybeLocal
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1430 procParams.append(param)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1431 prog.subroutines[self.op].inline(prog, procParams, output, otype, parent)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1432 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1433 output.append('\n\t' + self.op + '(' + ', '.join([str(p) for p in procParams]) + ');')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1434 prog.lastOp = self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1435
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1436 def processDispatch(self, prog):
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1437 if self.op == 'dispatch' and (len(self.params) == 1 or self.params[1] == 'main'):
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1438 prog.mainDispatch.add(self.params[0])
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1439
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1440 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1441 return '\n\t' + self.op + ' ' + ' '.join(self.params)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1442
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1443 #represents a DSL switch construct
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1444 class Switch(ChildBlock):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1445 def __init__(self, parent, param):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1446 self.op = 'switch'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1447 self.parent = parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1448 self.param = param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1449 self.cases = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1450 self.regValues = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1451 self.current_locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1452 self.case_locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1453 self.current_case = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1454 self.default = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1455 self.default_locals = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1456
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1457 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1458 if op.op == 'case':
2562 595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1459 if op.params[0].startswith('0x'):
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1460 val = int(op.params[0], 16)
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1461 elif op.params[0].startswith('0b'):
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1462 val = int(op.params[0], 2)
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1463 else:
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	1464 val = int(op.params[0])
1619 0e8438a4c76f Clean up warnings from -1 case Michael Pavone <pavone@retrodev.com> parents: 1618 diff changeset	1465 self.cases[val] = self.current_case = []
0e8438a4c76f Clean up warnings from -1 case Michael Pavone <pavone@retrodev.com> parents: 1618 diff changeset	1466 self.case_locals[val] = self.current_locals = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1467 elif op.op == 'default':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1468 self.default = self.current_case = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1469 self.default_locals = self.current_locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1470 elif self.current_case == None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1471 raise ion('Orphan instruction in switch')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1472 elif op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1473 name = op.params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1474 size = op.params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1475 self.current_locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1476 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1477 self.current_case.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1478
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1479 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1480 if name in self.current_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1481 return name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1482 return self.parent.resolveLocal(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1483
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1484 def addLocal(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1485 self.current_locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1486
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1487 def localSize(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1488 if name in self.current_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1489 return self.current_locals[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1490 return self.parent.localSize(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1491
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1492 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates):
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1493 prog.pushScope(self)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1494 param = prog.resolveParam(self.param, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1495 if type(param) is int:
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1496 self.regValues = self.parent.regValues
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1497 if param in self.cases:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1498 self.current_locals = self.case_locals[param]
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1499 output.append('\n\t{')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1500 for local in self.case_locals[param]:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1501 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[param][local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1502 self.processOps(prog, fieldVals, output, otype, self.cases[param])
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1503 output.append('\n\t}')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1504 elif self.default:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1505 self.current_locals = self.default_locals
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1506 output.append('\n\t{')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1507 for local in self.default_locals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1508 output.append('\n\tuint{0}_t {1};'.format(self.default[local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1509 self.processOps(prog, fieldVals, output, otype, self.default)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1510 output.append('\n\t}')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1511 else:
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1512 oldCond = prog.conditional
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1513 prog.conditional = True
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1514 output.append('\n\tswitch(' + param + ')')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1515 output.append('\n\t{')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1516 for case in self.cases:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1517 #temp = prog.temp.copy()
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1518 self.current_locals = self.case_locals[case]
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1519 self.regValues = dict(self.parent.regValues)
1619 0e8438a4c76f Clean up warnings from -1 case Michael Pavone <pavone@retrodev.com> parents: 1618 diff changeset	1520 output.append('\n\tcase {0}U: '.format(case) + '{')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1521 for local in self.case_locals[case]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1522 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[case][local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1523 self.processOps(prog, fieldVals, output, otype, self.cases[case])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1524 output.append('\n\tbreak;')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1525 output.append('\n\t}')
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1526 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1527 if self.default:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1528 #temp = prog.temp.copy()
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1529 self.current_locals = self.default_locals
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1530 self.regValues = dict(self.parent.regValues)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1531 output.append('\n\tdefault: {')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1532 for local in self.default_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1533 output.append('\n\tuint{0}_t {1};'.format(self.default_locals[local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1534 self.processOps(prog, fieldVals, output, otype, self.default)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1535 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1536 output.append('\n\t}')
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1537 prog.conditional = oldCond
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1538 prog.popScope()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1539
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1540 def processDispatch(self, prog):
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1541 for case in self.cases:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1542 for op in self.cases[case]:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1543 op.processDispatch(prog)
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1544 if self.default:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1545 for op in self.default:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1546 op.processDispatch(prog)
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1547
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1548 def __str__(self):
2704 c5dce4284e69 Fix a couple of bugs in CPU DSL found while working on uPD78K/II core Michael Pavone <pavone@retrodev.com> parents: 2680 diff changeset	1549 keys = list(self.cases.keys())
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1550 keys.sort()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1551 lines = ['\n\tswitch']
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1552 for case in keys:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1553 lines.append('\n\tcase {0}'.format(case))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1554 lines.append(''.join([str(op) for op in self.cases[case]]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1555 lines.append('\n\tend')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1556 return ''.join(lines)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1557
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1558
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1559 def _geuCImpl(prog, parent, fieldVals, output):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1560 if prog.lastOp.op == 'cmp':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1561 output.pop()
1616 8c78543c4783 Fix implementation cmp+condition version of if in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1615 diff changeset	1562 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params]
8c78543c4783 Fix implementation cmp+condition version of if in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1615 diff changeset	1563 return '\n\tif ({a} >= {b}) '.format(a=params[1], b = params[0]) + '{'
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1564 else:
1733 1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1565 raise Exception(">=U not implemented in the general case yet")
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1566
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1567 def _eqCImpl(prog, parent, fieldVals, output):
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1568 if prog.lastOp.op == 'cmp':
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1569 output.pop()
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1570 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1571 return '\n\tif ({a} == {b}) '.format(a=params[1], b = params[0]) + '{'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1572 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1573 return '\n\tif (!{a}) {{'.format(a=prog.resolveParam(prog.lastDst, None, {}))
1733 1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1574
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1575 def _neqCImpl(prog, parent, fieldVals, output):
2704 c5dce4284e69 Fix a couple of bugs in CPU DSL found while working on uPD78K/II core Michael Pavone <pavone@retrodev.com> parents: 2680 diff changeset	1576 if prog.lastOp.op == 'cmp':
c5dce4284e69 Fix a couple of bugs in CPU DSL found while working on uPD78K/II core Michael Pavone <pavone@retrodev.com> parents: 2680 diff changeset	1577 output.pop()
c5dce4284e69 Fix a couple of bugs in CPU DSL found while working on uPD78K/II core Michael Pavone <pavone@retrodev.com> parents: 2680 diff changeset	1578 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params]
c5dce4284e69 Fix a couple of bugs in CPU DSL found while working on uPD78K/II core Michael Pavone <pavone@retrodev.com> parents: 2680 diff changeset	1579 return '\n\tif ({a} != {b}) '.format(a=params[1], b = params[0]) + '{'
c5dce4284e69 Fix a couple of bugs in CPU DSL found while working on uPD78K/II core Michael Pavone <pavone@retrodev.com> parents: 2680 diff changeset	1580 else:
c5dce4284e69 Fix a couple of bugs in CPU DSL found while working on uPD78K/II core Michael Pavone <pavone@retrodev.com> parents: 2680 diff changeset	1581 return '\n\tif ({a}) {{'.format(a=prog.resolveParam(prog.lastDst, None, {}))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1582
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1583 _ifCmpImpl = {
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1584 'c': {
1733 1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1585 '>=U': _geuCImpl,
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1586 '=': _eqCImpl,
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1587 '!=': _neqCImpl
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1588 }
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1589 }
2452 8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1590 _ifCmpEval = {
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1591 '>=U': lambda a, b: a >= b,
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1592 '=': lambda a, b: a == b,
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1593 '!=': lambda a, b: a != b
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1594 }
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1595 #represents a DSL conditional construct
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1596 class If(ChildBlock):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1597 def __init__(self, parent, cond):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1598 self.op = 'if'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1599 self.parent = parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1600 self.cond = cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1601 self.body = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1602 self.elseBody = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1603 self.curBody = self.body
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1604 self.locals = {}
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1605 self.elseLocals = {}
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1606 self.curLocals = self.locals
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1607 self.regValues = None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1608
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1609 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1610 if op.op in ('case', 'arg'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1611 raise Exception(self.op + ' is not allows inside an if block')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1612 if op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1613 name = op.params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1614 size = op.params[1]
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1615 self.curLocals[name] = size
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1616 elif op.op == 'else':
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1617 self.curLocals = self.elseLocals
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1618 self.curBody = self.elseBody
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1619 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1620 self.curBody.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1621
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1622 def localSize(self, name):
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1623 return self.curLocals.get(name)
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1624
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1625 def resolveLocal(self, name):
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1626 if name in self.curLocals:
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1627 return name
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1628 return self.parent.resolveLocal(name)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1629
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1630 def _genTrueBody(self, prog, fieldVals, output, otype):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1631 self.curLocals = self.locals
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1632 subOut = []
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1633 self.processOps(prog, fieldVals, subOut, otype, self.body)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1634 for local in self.locals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1635 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.locals[local], nm=local))
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1636 output += subOut
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1637
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1638 def _genFalseBody(self, prog, fieldVals, output, otype):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1639 self.curLocals = self.elseLocals
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1640 subOut = []
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1641 self.processOps(prog, fieldVals, subOut, otype, self.elseBody)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1642 for local in self.elseLocals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1643 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.elseLocals[local], nm=local))
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1644 output += subOut
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1645
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1646 def _genConstParam(self, param, prog, fieldVals, output, otype):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1647 if param:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1648 self._genTrueBody(prog, fieldVals, output, otype)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1649 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1650 self._genFalseBody(prog, fieldVals, output, otype)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1651
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1652 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1653 self.regValues = parent.regValues
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1654 if self.cond in prog.booleans:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1655 self._genConstParam(prog.checkBool(self.cond), prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1656 else:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1657 if self.cond in _ifCmpImpl[otype]:
2452 8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1658 if prog.lastOp.op == 'cmp':
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1659 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params]
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1660 if type(params[0]) is int and type(params[1]) is int:
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1661 output.pop()
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1662 res = _ifCmpEval[self.cond](params[1], params[0])
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1663 self._genConstParam(res, prog, fieldVals, output, otype)
8b3daed1c076 Allow more if statements to be constant folded in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2451 diff changeset	1664 return
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1665 oldCond = prog.conditional
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1666 prog.conditional = True
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1667 #temp = prog.temp.copy()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1668 output.append(_ifCmpImpl[otype][self.cond](prog, parent, fieldVals, output))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1669 self._genTrueBody(prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1670 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1671 if self.elseBody:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1672 #temp = prog.temp.copy()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1673 output.append('\n\t} else {')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1674 self._genFalseBody(prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1675 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1676 output.append('\n\t}')
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1677 prog.conditional = oldCond
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1678 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1679 cond = prog.resolveParam(self.cond, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1680 if type(cond) is int:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1681 self._genConstParam(cond, prog, fieldVals, output, otype)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1682 else:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1683 #temp = prog.temp.copy()
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1684 output.append('\n\tif ({cond}) '.format(cond=cond) + '{')
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1685 oldCond = prog.conditional
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1686 prog.conditional = True
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1687 self._genTrueBody(prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1688 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1689 if self.elseBody:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1690 #temp = prog.temp.copy()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1691 output.append('\n\t} else {')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1692 self._genFalseBody(prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1693 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1694 output.append('\n\t}')
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1695 prog.conditional = oldCond
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1696
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1697
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1698 def processDispatch(self, prog):
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1699 for op in self.body:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1700 op.processDispatch(prog)
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1701 for op in self.elseBody:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1702 op.processDispatch(prog)
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	1703
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1704 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1705 lines = ['\n\tif']
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1706 for op in self.body:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1707 lines.append(str(op))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1708 lines.append('\n\tend')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1709 return ''.join(lines)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1710
2618 1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1711 class Loop(ChildBlock):
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1712 def __init__(self, parent, count):
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1713 self.op = 'loop'
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1714 self.parent = parent
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1715 self.count = count
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1716 self.body = []
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1717 self.locals = {}
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1718 self.regValues = None
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1719
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1720 def addOp(self, op):
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1721 if op.op in ('case', 'arg', 'else'):
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1722 raise Exception(op + ' is not allows inside an loop block')
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1723 if op.op == 'local':
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1724 name = op.params[0]
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1725 size = op.params[1]
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1726 self.locals[name] = size
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1727 else:
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1728 self.body.append(op)
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1729
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1730 def localSize(self, name):
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1731 return self.locals.get(name)
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1732
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1733 def resolveLocal(self, name):
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1734 if name in self.locals:
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1735 return name
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1736 return self.parent.resolveLocal(name)
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1737
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1738 def processDispatch(self, prog):
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1739 for op in self.body:
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1740 op.processDispatch(prog)
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1741
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1742 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates):
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1743 self.regValues = parent.regValues
2621 ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1744 for op in self.body:
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1745 if op.op in _opMap:
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1746 opDef = _opMap[op.op]
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1747 if len(opDef.outOp):
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1748 for index in opDef.outOp:
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1749 dst = op.params[index]
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1750 while dst in prog.meta:
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1751 dst = prog.meta[dst]
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1752 if dst in self.regValues:
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1753 #value changes in loop body
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1754 #so we need to prevent constant folding
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1755 maybeLocal = self.resolveLocal(dst)
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1756 if maybeLocal:
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1757 #for locals, we also need to persist
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1758 #the current constant fold value to the actual variable
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1759 output.append(f'\n\t{maybeLocal} = {self.regValues[dst]};')
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1760 del self.regValues[dst]
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1761 else:
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1762 #TODO: handle block types here
ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1763 pass
2618 1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1764 if self.count:
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1765 count = prog.resolveParam(self.count, self, fieldVals)
2621 ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1766 output.append(f'\n\tfor (uint32_t loop_counter__ = 0; loop_counter__ < {count}; loop_counter__++) {{')
2618 1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1767 else:
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1768 output.append('\n\tfor (;;) {')
2621 ce9386a7b21e Fix V flag for asl in new CPU core Michael Pavone <pavone@retrodev.com> parents: 2618 diff changeset	1769
2618 1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1770 self.processOps(prog, fieldVals, output, otype, self.body)
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1771 output.append('\n\t}')
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1772
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1773 def __str__(self):
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1774 lines = ['\n\tloop']
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1775 if self.count:
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1776 lines[0] += f' {self.count}'
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1777 for op in self.body:
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1778 lines.append(str(op))
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1779 lines.append('\n\tend')
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1780 return ''.join(lines)
1579b840a1af Implement stop in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2615 diff changeset	1781
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1782 class Registers:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1783 def __init__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1784 self.regs = {}
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1785 self.pointers = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1786 self.regArrays = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1787 self.regToArray = {}
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1788 self.addReg('cycles', 32)
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	1789 self.addReg('sync_cycle', 32)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1790
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1791 def addReg(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1792 self.regs[name] = size
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1793
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1794 def addPointer(self, name, size, count):
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1795 self.pointers[name] = (size, count)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1796
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1797 def addRegArray(self, name, size, regs):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1798 self.regArrays[name] = (size, regs)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1799 idx = 0
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1800 if not type(regs) is int:
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1801 for reg in regs:
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1802 self.regs[reg] = size
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1803 self.regToArray[reg] = (name, idx)
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1804 idx += 1
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1805
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1806 def isReg(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1807 return name in self.regs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1808
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1809 def isRegArray(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1810 return name in self.regArrays
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1811
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1812 def isRegArrayMember(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1813 return name in self.regToArray
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1814
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1815 def arrayMemberParent(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1816 return self.regToArray[name][0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1817
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1818 def arrayMemberIndex(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1819 return self.regToArray[name][1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1820
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1821 def arrayMemberName(self, array, index):
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1822 if type(index) is int and not type(self.regArrays[array][1]) is int:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1823 return self.regArrays[array][1][index]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1824 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1825 return None
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1826
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1827 def isNamedArray(self, array):
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1828 return array in self.regArrays and type(self.regArrays[array][1]) is int
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1829
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1830 def processLine(self, parts):
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1831 if len(parts) == 3:
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1832 if parts[1].startswith('ptr'):
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1833 self.addPointer(parts[0], parts[1][3:], int(parts[2]))
2666 38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints Michael Pavone <pavone@retrodev.com> parents: 2637 diff changeset	1834 elif parts[1].isdigit():
38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints Michael Pavone <pavone@retrodev.com> parents: 2637 diff changeset	1835 self.addRegArray(parts[0], int(parts[1]), int(parts[2]))
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1836 else:
2666 38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints Michael Pavone <pavone@retrodev.com> parents: 2637 diff changeset	1837 #assume some other C type
38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints Michael Pavone <pavone@retrodev.com> parents: 2637 diff changeset	1838 self.addRegArray(parts[0], parts[1], int(parts[2]))
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1839 elif len(parts) > 2:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1840 self.addRegArray(parts[0], int(parts[1]), parts[2:])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1841 else:
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1842 if parts[1].startswith('ptr'):
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1843 self.addPointer(parts[0], parts[1][3:], 1)
2666 38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints Michael Pavone <pavone@retrodev.com> parents: 2637 diff changeset	1844 elif parts[1].isdigit():
38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints Michael Pavone <pavone@retrodev.com> parents: 2637 diff changeset	1845 self.addReg(parts[0], int(parts[1]))
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1846 else:
2666 38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints Michael Pavone <pavone@retrodev.com> parents: 2637 diff changeset	1847 #assume some other C type
38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints Michael Pavone <pavone@retrodev.com> parents: 2637 diff changeset	1848 self.addReg(parts[0], parts[1])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1849 return self
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1850
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1851 def writeHeader(self, otype, hFile):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1852 fieldList = []
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1853 for pointer in self.pointers:
1735 ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1854 stars = '*'
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1855 ptype, count = self.pointers[pointer]
1735 ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1856 while ptype.startswith('ptr'):
ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1857 stars += '*'
ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1858 ptype = ptype[3:]
ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1859 if ptype.isdigit():
ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1860 ptype = 'uint{sz}_t'.format(sz=ptype)
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1861 if count > 1:
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1862 arr = '[{n}]'.format(n=count)
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1863 else:
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1864 arr = ''
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1865 hFile.write('\n\t{ptype} {stars}{nm}{arr};'.format(nm=pointer, ptype=ptype, stars=stars, arr=arr))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1866 for reg in self.regs:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1867 if not self.isRegArrayMember(reg):
2666 38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints Michael Pavone <pavone@retrodev.com> parents: 2637 diff changeset	1868 if type(self.regs[reg]) is int:
38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints Michael Pavone <pavone@retrodev.com> parents: 2637 diff changeset	1869 fieldList.append((self.regs[reg], 1, reg))
38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints Michael Pavone <pavone@retrodev.com> parents: 2637 diff changeset	1870 else:
38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints Michael Pavone <pavone@retrodev.com> parents: 2637 diff changeset	1871 hFile.write(f'\n\t{self.regs[reg]} {reg};')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1872 for arr in self.regArrays:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1873 size,regs = self.regArrays[arr]
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1874 if not type(regs) is int:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1875 regs = len(regs)
2666 38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints Michael Pavone <pavone@retrodev.com> parents: 2637 diff changeset	1876 if not type(size) is int:
38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints Michael Pavone <pavone@retrodev.com> parents: 2637 diff changeset	1877 hFile.write(f'\n\t{size} {arr}[{regs}];')
38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints Michael Pavone <pavone@retrodev.com> parents: 2637 diff changeset	1878 continue
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1879 fieldList.append((size, regs, arr))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1880 fieldList.sort()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1881 fieldList.reverse()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1882 for size, count, name in fieldList:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1883 if count > 1:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1884 hFile.write('\n\tuint{sz}_t {nm}[{ct}];'.format(sz=size, nm=name, ct=count))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1885 else:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1886 hFile.write('\n\tuint{sz}_t {nm};'.format(sz=size, nm=name))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1887
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1888 class Flags:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1889 def __init__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1890 self.flagBits = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1891 self.flagCalc = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1892 self.flagStorage = {}
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1893 self.flagOrder = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1894 self.flagReg = None
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	1895 self.storageToFlags = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1896 self.maxBit = -1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1897
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1898 def processLine(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1899 if parts[0] == 'register':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1900 self.flagReg = parts[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1901 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1902 flag,bit,calc,storage = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1903 bit,_,top = bit.partition('-')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1904 bit = int(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1905 if top:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1906 top = int(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1907 if top > self.maxBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1908 self.maxBit = top
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1909 self.flagBits[flag] = (bit,top)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1910 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1911 if bit > self.maxBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1912 self.maxBit = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1913 self.flagBits[flag] = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1914 self.flagCalc[flag] = calc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1915 self.flagStorage[flag] = storage
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	1916 storage,_,storebit = storage.partition('.')
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	1917 self.storageToFlags.setdefault(storage, []).append((storebit, flag))
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1918 self.flagOrder.append(flag)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1919 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1920
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1921 def getStorage(self, flag):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1922 if not flag in self.flagStorage:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1923 raise Exception('Undefined flag ' + flag)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1924 loc,_,bit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1925 if bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1926 return (loc, int(bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1927 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1928 return loc
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1929
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1930 def parseFlagUpdate(self, flagString):
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1931 last = ''
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1932 autoUpdate = set()
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1933 explicit = {}
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1934 for c in flagString:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1935 if c.isdigit():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1936 if last.isalpha():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1937 num = int(c)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1938 if num > 1:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1939 raise Exception(c + ' is not a valid digit for update_flags')
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1940 explicit[last] = num
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1941 last = c
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1942 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1943 raise Exception('Digit must follow flag letter in update_flags')
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1944 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1945 if last.isalpha():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1946 autoUpdate.add(last)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1947 last = c
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1948 if last.isalpha():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1949 autoUpdate.add(last)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1950 return (autoUpdate, explicit)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1951
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1952 def disperseFlags(self, prog, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1953 bitToFlag = [None] * (self.maxBit+1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1954 src = prog.resolveReg(self.flagReg, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1955 output = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1956 for flag in self.flagBits:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1957 bit = self.flagBits[flag]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1958 if type(bit) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1959 bot,top = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1960 mask = ((1 << (top + 1 - bot)) - 1) << bot
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1961 output.append('\n\t{dst} = {src} & mask;'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1962 dst=prog.resolveReg(self.flagStorage[flag], None, {}), src=src, mask=mask
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1963 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1964 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1965 bitToFlag[self.flagBits[flag]] = flag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1966 multi = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1967 for bit in range(len(bitToFlag)-1,-1,-1):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1968 flag = bitToFlag[bit]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1969 if not flag is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1970 field,_,dstbit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1971 dst = prog.resolveReg(field, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1972 if dstbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1973 dstbit = int(dstbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1974 multi.setdefault(dst, []).append((dstbit, bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1975 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1976 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=(1 << bit)))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1977 for dst in multi:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1978 didClear = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1979 direct = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1980 for dstbit, bit in multi[dst]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1981 if dstbit == bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1982 direct.append(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1983 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1984 if not didClear:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1985 output.append('\n\t{dst} = 0;'.format(dst=dst))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1986 didClear = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1987 if dstbit > bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1988 shift = '<<'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1989 diff = dstbit - bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1990 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1991 shift = '>>'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1992 diff = bit - dstbit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1993 output.append('\n\t{dst} \|= {src} {shift} {diff} & {mask};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1994 src=src, dst=dst, shift=shift, diff=diff, mask=(1 << dstbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1995 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1996 if direct:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1997 if len(direct) == len(multi[dst]):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1998 output.append('\n\t{dst} = {src};'.format(dst=dst, src=src))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1999 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2000 mask = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2001 for bit in direct:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2002 mask = mask \| (1 << bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2003 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=mask))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2004 return ''.join(output)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2005
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2006 def coalesceFlags(self, prog, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2007 dst = prog.resolveReg(self.flagReg, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2008 output = ['\n\t{dst} = 0;'.format(dst=dst)]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2009 bitToFlag = [None] * (self.maxBit+1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2010 for flag in self.flagBits:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2011 bit = self.flagBits[flag]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2012 if type(bit) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2013 bot,_ = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2014 src = prog.resolveReg(self.flagStorage[flag], None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2015 if bot:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2016 output.append('\n\t{dst} \|= {src} << {shift};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2017 dst=dst, src = src, shift = bot
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2018 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2019 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2020 output.append('\n\t{dst} \|= {src};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2021 dst=dst, src = src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2022 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2023 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2024 bitToFlag[bit] = flag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2025 multi = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2026 for bit in range(len(bitToFlag)-1,-1,-1):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2027 flag = bitToFlag[bit]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2028 if not flag is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2029 field,_,srcbit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2030 src = prog.resolveReg(field, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2031 if srcbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2032 srcbit = int(srcbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2033 multi.setdefault(src, []).append((srcbit,bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2034 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2035 output.append('\n\tif ({src}) {{\n\t\t{dst} \|= 1 << {bit};\n\t}}'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2036 dst=dst, src=src, bit=bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2037 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2038 for src in multi:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2039 direct = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2040 for srcbit, dstbit in multi[src]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2041 if srcbit == dstbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2042 direct = direct \| (1 << srcbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2043 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2044 output.append('\n\tif ({src} & (1 << {srcbit})) {{\n\t\t{dst} \|= 1 << {dstbit};\n\t}}'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2045 src=src, dst=dst, srcbit=srcbit, dstbit=dstbit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2046 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2047 if direct:
1698 90272218469c Fixed missing semicolon in coalesceFlags Michael Pavone <pavone@retrodev.com> parents: 1697 diff changeset	2048 output.append('\n\t{dst} \|= {src} & {mask};'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2049 dst=dst, src=src, mask=direct
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2050 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2051 return ''.join(output)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2052
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2053
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2054 class Program:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2055 def __init__(self, regs, instructions, subs, info, flags):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2056 self.regs = regs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2057 self.instructions = instructions
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2058 self.subroutines = subs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2059 self.meta = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2060 self.booleans = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2061 self.prefix = info.get('prefix', [''])[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2062 self.opsize = int(info.get('opcode_size', ['8'])[0])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2063 self.extra_tables = info.get('extra_tables', [])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2064 self.context_type = self.prefix + 'context'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2065 self.body = info.get('body', [None])[0]
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	2066 self.interrupt = info.get('interrupt', [None])[0]
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	2067 self.sync_cycle = info.get('sync_cycle', [None])[0]
1620 a172f97d873f Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16 Michael Pavone <pavone@retrodev.com> parents: 1619 diff changeset	2068 self.includes = info.get('include', [])
2676 7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2069 self.pc_reg = info.get('pc_reg', [None])[0]
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2070 self.pc_offset = info.get('pc_offset', [0])[0]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2071 self.flags = flags
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2072 self.lastDst = None
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2073 self.scopes = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2074 self.currentScope = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2075 self.lastOp = None
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	2076 self.carryFlowDst = None
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	2077 self.lastA = None
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	2078 self.lastB = None
1708 5bfed2eedc9d Fixed flag calculation for sub instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1707 diff changeset	2079 self.lastBFlow = None
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2080 self.sizeAdjust = None
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	2081 self.conditional = False
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2082 self.declares = []
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2083 self.lastSize = None
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2084 self.mainDispatch = set()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2085
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2086 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2087 pieces = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2088 for reg in self.regs:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2089 pieces.append(str(self.regs[reg]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2090 for name in self.subroutines:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2091 pieces.append('\n'+str(self.subroutines[name]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2092 for instruction in self.instructions:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2093 pieces.append('\n'+str(instruction))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2094 return ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2095
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2096 def writeHeader(self, otype, header):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2097 hFile = open(header, 'w')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2098 macro = header.upper().replace('.', '_')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2099 hFile.write('#ifndef {0}_'.format(macro))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2100 hFile.write('\n#define {0}_'.format(macro))
2500 d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	2101 hFile.write('\n#include <stdio.h>')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2102 hFile.write('\n#include "backend.h"')
2676 7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2103 if self.pc_reg:
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2104 hFile.write('\n#include "tern.h"')
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	2105 hFile.write(f'\n\ntypedef struct {self.prefix}options {self.prefix}options;')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	2106 hFile.write(f'\n\ntypedef struct {self.prefix}context {self.prefix}context;')
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2107 for decl in self.declares:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2497 diff changeset	2108 if decl.startswith('define '):
d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2497 diff changeset	2109 decl = '#' + decl
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2110 hFile.write('\n' + decl)
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	2111 hFile.write(f'\n\nstruct {self.prefix}options {{')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	2112 hFile.write('\n\tcpu_options gen;')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	2113 hFile.write('\n\tFILE* address_log;')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	2114 hFile.write('\n};')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	2115 hFile.write(f'\n\nstruct {self.prefix}context {{')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	2116 hFile.write(f'\n\t{self.prefix}options *opts;')
2676 7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2117 if self.pc_reg:
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2118 hFile.write('\n\ttern_node *breakpoints;');
2577 5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	2119 self.regs.writeHeader(otype, hFile)
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	2120 hFile.write('\n};')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	2121 hFile.write('\n')
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional Michael Pavone <pavone@retrodev.com> parents: 2562 diff changeset	2122 hFile.write('\nvoid {pre}execute({type} *context, uint32_t target_cycle);'.format(pre = self.prefix, type = self.context_type))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2123 hFile.write('\n#endif //{0}_'.format(macro))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2124 hFile.write('\n')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2125 hFile.close()
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	2126
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2127 def _buildTable(self, otype, table, body, lateBody):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2128 pieces = []
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	2129 opmap = [None] * (1 << self.opsize)
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	2130 bodymap = {}
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	2131 if table in self.instructions:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2132 instructions = self.instructions[table]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2133 instructions.sort()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2134 for inst in instructions:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2135 for val in inst.allValues():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2136 if opmap[val] is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2137 self.meta = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2138 self.temp = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2139 self.needFlagCoalesce = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2140 self.needFlagDisperse = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2141 self.lastOp = None
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2142 name = inst.generateName(val)
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2143 opmap[val] = name
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2144 if not name in bodymap:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2145 bodymap[name] = inst.generateBody(val, self, otype)
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	2146
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2147 alreadyAppended = set()
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2148 if self.dispatch == 'call':
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2149 lateBody.append('\nstatic impl_fun impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap)))
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2150 for inst in range(0, len(opmap)):
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2151 op = opmap[inst]
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2152 if op is None:
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2153 lateBody.append('\n\tunimplemented,')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2154 else:
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2155 lateBody.append('\n\t' + op + ',')
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2156 if not op in alreadyAppended:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2157 body.append(bodymap[op])
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2158 alreadyAppended.add(op)
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2159 lateBody.append('\n};')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2160 elif self.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2161 body.append('\n\tstatic void *impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap)))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2162 for inst in range(0, len(opmap)):
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2163 op = opmap[inst]
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2164 if op is None:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2165 body.append('\n\t\t&&unimplemented,')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2166 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2167 body.append('\n\t\t&&' + op + ',')
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2168 if not op in alreadyAppended:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2169 lateBody.append(bodymap[op])
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2170 body.append('\n\t};')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2171 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2172 raise Exception("unimplmeneted dispatch type " + self.dispatch)
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	2173 body.extend(pieces)
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2174
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2175 def nextInstruction(self, otype):
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2176 output = []
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2177 if self.dispatch == 'goto':
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	2178 if self.interrupt in self.subroutines:
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	2179 output.append('\n\tif (context->cycles >= context->sync_cycle) {')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2180 output.append('\n\tif (context->cycles >= target_cycle) { return; }')
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	2181 if self.interrupt in self.subroutines:
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	2182 self.meta = {}
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	2183 self.temp = {}
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	2184 self.subroutines[self.interrupt].inline(self, [], output, otype, None)
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	2185 output.append('\n\t}')
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	2186
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2187 self.meta = {}
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2188 self.temp = {}
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2189 self.subroutines[self.body].inline(self, [], output, otype, None)
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2190 return output
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	2191
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	2192 def build(self, otype):
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	2193 body = []
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	2194 pieces = []
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	2195 for include in self.includes:
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	2196 body.append('#include "{0}"\n'.format(include))
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2197 if self.dispatch == 'call':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2198 body.append('\ntypedef void (impl_fun)({pre}context context, uint32_t target_cycle);'.format(pre=self.prefix))
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2199 for table in self.extra_tables:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2200 body.append('\nstatic impl_fun impl_{name}[{sz}];'.format(name = table, sz=(1 << self.opsize)))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2201 body.append('\nstatic impl_fun impl_main[{sz}];'.format(sz=(1 << self.opsize)))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2202 elif self.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2203 body.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2204 body.append('\n{')
2591 563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2205
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2206 for table in self.instructions:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2207 for inst in self.instructions[table]:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2208 inst.processDispatch(self)
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2209 for sub in self.subroutines:
563d05355a12 Cut down on code bloat in 68K core a little Michael Pavone <pavone@retrodev.com> parents: 2589 diff changeset	2210 self.subroutines[sub].processDispatch(self)
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2211
1740 28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL Michael Pavone <pavone@retrodev.com> parents: 1737 diff changeset	2212 for table in self.extra_tables:
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2213 self._buildTable(otype, table, body, pieces)
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2214 self._buildTable(otype, 'main', body, pieces)
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2215 if self.dispatch == 'call':
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2216 if self.body in self.subroutines:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2217 pieces.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type))
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2218 pieces.append('\n{')
2704 c5dce4284e69 Fix a couple of bugs in CPU DSL found while working on uPD78K/II core Michael Pavone <pavone@retrodev.com> parents: 2680 diff changeset	2219 if self.sync_cycle:
c5dce4284e69 Fix a couple of bugs in CPU DSL found while working on uPD78K/II core Michael Pavone <pavone@retrodev.com> parents: 2680 diff changeset	2220 pieces.append('\n\t{sync}(context, target_cycle);'.format(sync=self.sync_cycle))
2676 7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2221 if self.pc_reg:
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2222 pieces.append('\n\tif (context->breakpoints) {')
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2223 pieces.append('\n\t\twhile (context->cycles < target_cycle)')
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2224 pieces.append('\n\t\t{')
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2225 if self.interrupt in self.subroutines:
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2226 pieces.append('\n\t\t\tif (context->cycles >= context->sync_cycle) {')
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2227 pieces.append(f'\n\t\t\t\t{self.sync_cycle}(context, target_cycle);')
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2228 pieces.append('\n\t\t\t}')
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2229 self.meta = {}
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2230 self.temp = {}
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2231 intpieces = []
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2232 self.subroutines[self.interrupt].inline(self, [], intpieces, otype, None)
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2233 for size in self.temp:
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2234 pieces.append('\n\t\t\tuint{sz}_t gen_tmp{sz}__;'.format(sz=size))
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2235 pieces += intpieces
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2236 if self.pc_offset:
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2237 pieces.append(f'\n\t\t\tuint32_t debug_pc = context->{self.pc_reg} - {self.pc_offset};')
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2238 pc_reg = 'debug_pc'
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2239 else:
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2240 pc_reg = 'context->' + self.pc_reg
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2241 pieces.append('\n\t\t\tchar key_buf[6];')
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2242 pieces.append(f'\n\t\t\tdebug_handler handler = tern_find_ptr(context->breakpoints, tern_int_key({pc_reg}, key_buf));')
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2243 pieces.append('\n\t\t\tif (handler) {')
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2244 pieces.append(f'\n\t\t\t\thandler(context, {pc_reg});')
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2245 pieces.append('\n\t\t\t}')
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2246 self.meta = {}
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2247 self.temp = {}
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2248 self.subroutines[self.body].inline(self, [], pieces, otype, None)
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2249 pieces.append('\n\t}')
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2250 pieces.append('\n\t} else {')
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2251 pieces.append('\n\twhile (context->cycles < target_cycle)')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2252 pieces.append('\n\t{')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2253 if self.interrupt in self.subroutines:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2254 pieces.append('\n\t\tif (context->cycles >= context->sync_cycle) {')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2255 pieces.append(f'\n\t\t\t{self.sync_cycle}(context, target_cycle);')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2256 pieces.append('\n\t\t}')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2257 self.meta = {}
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2258 self.temp = {}
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2259 intpieces = []
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2260 self.subroutines[self.interrupt].inline(self, [], intpieces, otype, None)
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2261 for size in self.temp:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2262 pieces.append('\n\tuint{sz}_t gen_tmp{sz}__;'.format(sz=size))
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2263 pieces += intpieces
1883 9ab5184811ea Implement interrupts in call dispatch mode in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1838 diff changeset	2264 self.meta = {}
9ab5184811ea Implement interrupts in call dispatch mode in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1838 diff changeset	2265 self.temp = {}
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2266 self.subroutines[self.body].inline(self, [], pieces, otype, None)
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2267 pieces.append('\n\t}')
2676 7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2268 if self.pc_reg:
7e86ec94c899 Implement breakpoints in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2672 diff changeset	2269 pieces.append('\n\t}')
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2270 pieces.append('\n}')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2271 body.append('\nstatic void unimplemented({pre}context *context, uint32_t target_cycle)'.format(pre = self.prefix))
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2272 body.append('\n{')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2273 if len(self.mainDispatch) == 1:
2592 8ef8b2e99f4f Fix regression in better unimplemented instruction error in CPU dsl Michael Pavone <pavone@retrodev.com> parents: 2591 diff changeset	2274 dispatch = self.resolveParam(list(self.mainDispatch)[0], None, {})
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2275 body.append(f'\n\tfatal_error("Unimplemented instruction: %X\\n", {dispatch});')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2276 else:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2277 body.append('\n\tfatal_error("Unimplemented instruction\\n");')
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2278 body.append('\n}\n')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2279 elif self.dispatch == 'goto':
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	2280 body.append('\n\t{sync}(context, target_cycle);'.format(sync=self.sync_cycle))
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2281 body += self.nextInstruction(otype)
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2282 pieces.append('\nunimplemented:')
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2283 if len(self.mainDispatch) == 1:
9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2284 dispatch = list(self.mainDispatch)[0]
2680 e3394457427e Fix small bug in goto dispatch output of CPU dsl Michael Pavone <pavone@retrodev.com> parents: 2676 diff changeset	2285 pieces.append(f'\n\tfatal_error("Unimplemented instruction: %X\\n", {dispatch});')
2581 9e10149c9e10 Better unimplemented instruction error message in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2580 diff changeset	2286 else:
2680 e3394457427e Fix small bug in goto dispatch output of CPU dsl Michael Pavone <pavone@retrodev.com> parents: 2676 diff changeset	2287 pieces.append('\n\tfatal_error("Unimplemented instruction\\n");')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2288 pieces.append('\n}')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2289 return ''.join(body) + ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2290
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2291 def checkBool(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2292 if not name in self.booleans:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2293 raise Exception(name + ' is not a defined boolean flag')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2294 return self.booleans[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2295
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2296 def getTemp(self, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2297 if size in self.temp:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2298 return ('', self.temp[size])
1742 6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1740 diff changeset	2299 self.temp[size] = 'gen_tmp{sz}__'.format(sz=size);
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2300 return ('', self.temp[size])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2301
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2302 def resolveParam(self, param, parent, fieldVals, allowConstant=True, isdst=False):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2303 keepGoing = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2304 while keepGoing:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2305 keepGoing = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2306 try:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2307 if type(param) is int:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2308 pass
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2309 elif param.startswith('0x'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2310 param = int(param, 16)
2562 595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	2311 elif param.startswith('0b'):
595719fe69f2 Implement exg, muls and mulu in new 68K core Michael Pavone <pavone@retrodev.com> parents: 2502 diff changeset	2312 param = int(param, 2)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2313 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2314 param = int(param)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2315 except ValueError:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2316
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2317 if parent:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2318 if param in parent.regValues and allowConstant:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2319 return parent.regValues[param]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2320 maybeLocal = parent.resolveLocal(param)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2321 if maybeLocal:
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2322 if isdst:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2323 self.lastDst = param
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2324 self.lastSize = None
2615 cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	2325 if allowConstant and maybeLocal in parent.regValues:
cbd54de385d3 Fix some issues with constant folding in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 2611 diff changeset	2326 return parent.regValues[maybeLocal]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2327 return maybeLocal
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2328 if param in fieldVals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2329 param = fieldVals[param]
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	2330 fieldVals = {}
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	2331 keepGoing = True
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2332 elif param in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2333 param = self.meta[param]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2334 keepGoing = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2335 elif self.isReg(param):
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2336 return self.resolveReg(param, parent, fieldVals, isdst)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2337 elif param in self.regs.pointers:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2338 return 'context->' + param
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2339 if isdst:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2340 self.lastDst = param
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2341 self.lastSize = None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2342 return param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2343
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2344 def isReg(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2345 if not type(name) is str:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2346 return False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2347 begin,sep,_ = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2348 if sep:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2349 if begin in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2350 begin = self.meta[begin]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2351 return self.regs.isRegArray(begin)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2352 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2353 return self.regs.isReg(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2354
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2355 def resolveReg(self, name, parent, fieldVals, isDst=False):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2356 begin,sep,end = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2357 if sep:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2358 if begin in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2359 begin = self.meta[begin]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2360 if not self.regs.isRegArrayMember(end):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2361 end = self.resolveParam(end, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2362 if not type(end) is int and self.regs.isRegArrayMember(end):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2363 arrayName = self.regs.arrayMemberParent(end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2364 end = self.regs.arrayMemberIndex(end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2365 if arrayName != begin:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2366 end = 'context->{0}[{1}]'.format(arrayName, end)
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	2367 if self.regs.isNamedArray(begin):
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	2368 regName = self.regs.arrayMemberName(begin, end)
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	2369 else:
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	2370 regName = '{0}.{1}'.format(begin, end)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2371 ret = 'context->{0}[{1}]'.format(begin, end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2372 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2373 regName = name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2374 if self.regs.isRegArrayMember(name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2375 arr,idx = self.regs.regToArray[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2376 ret = 'context->{0}[{1}]'.format(arr, idx)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2377 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2378 ret = 'context->' + name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2379 if regName == self.flags.flagReg:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2380 if isDst:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2381 self.needFlagDisperse = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2382 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2383 self.needFlagCoalesce = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2384 if isDst:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2385 self.lastDst = regName
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2386 return ret
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2387
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2388
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2389
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2390 def paramSize(self, name):
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2391 if name in self.meta:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2392 return self.paramSize(self.meta[name])
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2393 for i in range(len(self.scopes) -1, -1, -1):
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2394 size = self.scopes[i].localSize(name)
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2395 if size:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	2396 return size
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2397 begin,sep,_ = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2398 if sep and self.regs.isRegArray(begin):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2399 return self.regs.regArrays[begin][0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2400 if self.regs.isReg(name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2401 return self.regs.regs[name]
2610 2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	2402 for size in self.temp:
2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	2403 if self.temp[size] == name:
2de52352936c Fix lsl in new CPU core and make asl less broken Michael Pavone <pavone@retrodev.com> parents: 2609 diff changeset	2404 return size
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2405 return 32
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2406
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2407 def getLastSize(self):
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2408 if self.lastSize:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2409 return self.lastSize
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2410 return self.paramSize(self.lastDst)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	2411
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2412 def pushScope(self, scope):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2413 self.scopes.append(scope)
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2414 self.currentScope = scope
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2415
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2416 def popScope(self):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2417 ret = self.scopes.pop()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2418 self.currentScope = self.scopes[-1] if self.scopes else None
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2419 return ret
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2420
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2421 def getRootScope(self):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2422 return self.scopes[0]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2423
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2424 def parse(args):
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2425 f = args.source
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2426 instructions = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2427 subroutines = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2428 registers = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2429 flags = None
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2430 declares = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2431 errors = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2432 info = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2433 line_num = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2434 cur_object = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2435 for line in f:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2436 line_num += 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2437 line,_,comment = line.partition('#')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2438 if not line.strip():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2439 continue
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2440 if line[0].isspace():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2441 if not cur_object is None:
1754 043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2442 sep = True
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2443 parts = []
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2444 while sep:
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2445 before,sep,after = line.partition('"')
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2446 before = before.strip()
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2447 if before:
2440 338c78da3fff Added a little syntax sugar to CPU DSL and started updating new Z80 core to use it Michael Pavone <pavone@retrodev.com> parents: 1991 diff changeset	2448 parts += [el.strip() for el in before.split(' ') if el.strip()]
1754 043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2449 if sep:
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2450 #TODO: deal with escaped quotes
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2451 inside,sep,after = after.partition('"')
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2452 parts.append('"' + inside + '"')
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2453 line = after
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2454 if type(cur_object) is dict:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2455 cur_object[parts[0]] = parts[1:]
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2456 elif type(cur_object) is list:
1754 043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	2457 cur_object.append(' '.join(parts))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2458 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2459 cur_object = cur_object.processLine(parts)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2460
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2461 # if type(cur_object) is Registers:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2462 # if len(parts) > 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2463 # cur_object.addRegArray(parts[0], int(parts[1]), parts[2:])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2464 # else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2465 # cur_object.addReg(parts[0], int(parts[1]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2466 # elif type(cur_object) is dict:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2467 # cur_object[parts[0]] = parts[1:]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2468 # elif parts[0] == 'switch':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2469 # o = Switch(cur_object, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2470 # cur_object.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2471 # cur_object = o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2472 # elif parts[0] == 'if':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2473 # o = If(cur_object, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2474 # cur_object.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2475 # cur_object = o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2476 # elif parts[0] == 'end':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2477 # cur_object = cur_object.parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2478 # else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2479 # cur_object.addOp(NormalOp(parts))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2480 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2481 errors.append("Orphan instruction on line {0}".format(line_num))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2482 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2483 parts = line.split(' ')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2484 if len(parts) > 1:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2485 if len(parts) > 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2486 table,bitpattern,name = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2487 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2488 bitpattern,name = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2489 table = 'main'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2490 value = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2491 fields = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2492 curbit = len(bitpattern) - 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2493 for char in bitpattern:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2494 value <<= 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2495 if char in ('0', '1'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2496 value \|= int(char)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2497 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2498 if char in fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2499 fields[char] = (curbit, fields[char][1] + 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2500 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2501 fields[char] = (curbit, 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2502 curbit -= 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2503 cur_object = Instruction(value, fields, name.strip())
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2504 instructions.setdefault(table, []).append(cur_object)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2505 elif line.strip() == 'regs':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2506 if registers is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2507 registers = Registers()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2508 cur_object = registers
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2509 elif line.strip() == 'info':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2510 cur_object = info
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2511 elif line.strip() == 'flags':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2512 if flags is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2513 flags = Flags()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2514 cur_object = flags
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2515 elif line.strip() == 'declare':
48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2516 cur_object = declares
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2517 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2518 cur_object = SubRoutine(line.strip())
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2519 subroutines[cur_object.name] = cur_object
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2520 if errors:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2521 print(errors)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2522 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2523 p = Program(registers, instructions, subroutines, info, flags)
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2524 p.dispatch = args.dispatch
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	2525 p.declares = declares
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2526 p.booleans['dynarec'] = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2527 p.booleans['interp'] = True
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2528 if args.define:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2529 for define in args.define:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2530 name,sep,val = define.partition('=')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2531 name = name.strip()
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2532 val = val.strip()
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2533 if sep:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2534 p.booleans[name] = bool(val)
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2535 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2536 p.booleans[name] = True
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2537
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2538 if 'header' in info:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2539 print('#include "{0}"'.format(info['header'][0]))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2540 p.writeHeader('c', info['header'][0])
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2541 print('#include "util.h"')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	2542 print('#include <stdlib.h>')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2543 print(p.build('c'))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2544
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2545 def main(argv):
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2546 from argparse import ArgumentParser, FileType
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2547 argParser = ArgumentParser(description='CPU emulator DSL compiler')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2548 argParser.add_argument('source', type=FileType('r'))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2549 argParser.add_argument('-D', '--define', action='append')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2550 argParser.add_argument('-d', '--dispatch', choices=('call', 'switch', 'goto'), default='call')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	2551 parse(argParser.parse_args(argv[1:]))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2552
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2553 if __name__ == '__main__':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2554 from sys import argv
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2555 main(argv)

Mercurial > repos > blastem

annotate cpu_dsl.py @ 2707:a64c0e1ed6ac default tip