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comparison analyze.py @ 428:006008a3f370

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Last set of changes to analyze.py from when I was last working on reversing the VDP
author Mike Pavone <pavone@retrodev.com>
date Sun, 07 Jul 2013 15:05:50 -0700
parents b231162c8fdd
children
comparison
equal deleted inserted replaced
427:2802318c14e1 428:006008a3f370
1 #!/usr/bin/env python 1 #!/usr/bin/env python
2 2
3 #OLD
3 #0 - !SE 4 #0 - !SE
4 #1 - !CAS 5 #1 - !CAS
5 #2 - A0 6 #2 - A0
6 #3 - A1 7 #3 - A1
7 #------ 8 #------
9 #5 - A3 10 #5 - A3
10 #6 - A7 11 #6 - A7
11 #7 - EDCLK 12 #7 - EDCLK
12 #------ 13 #------
13 #8 - !HSYNC 14 #8 - !HSYNC
15 #9 - A4
16 #A - A5
17 #B - A6
18 #------
19 #C - !RAS
20 #D - !WB/!WE
21 #E - !DT/!OE
22 #F - SC
23
24 #NEW
25 #0 - !IPL2
26 #1 - !CAS
27 #2 - A0
28 #3 - A1
29 #------
30 #4 - A2
31 #5 - A3
32 #6 - A7
33 #7 - !HSYNC
34 #------
35 #8 - !VSYNC
14 #9 - A4 36 #9 - A4
15 #A - A5 37 #A - A5
16 #B - A6 38 #B - A6
17 #------ 39 #------
18 #C - !RAS 40 #C - !RAS
61 def detect_high(sample, bit): 83 def detect_high(sample, bit):
62 mask = 1 << bit 84 mask = 1 << bit
63 return sample & mask 85 return sample & mask
64 86
65 87
88 ipl2 = 0x0
66 cas = 0x1 89 cas = 0x1
67 ras = 0xC 90 ras = 0xC
68 edclk = 0x7 91 vsync = 0x8
69 hsync = 0x8 92 hsync = 0x7
70 wewb = 0xD 93 wewb = 0xD
71 oedt = 0xE 94 oedt = 0xE
72 sc = 0xF 95 sc = 0xF
73 96
74 last = False 97 last = False
101 rate = (1.0/float(rate.strip())) * 1000000000.0 124 rate = (1.0/float(rate.strip())) * 1000000000.0
102 elif not line.startswith(';'): 125 elif not line.startswith(';'):
103 sample,_,samplenum = line.partition('@') 126 sample,_,samplenum = line.partition('@')
104 samplenum = int(samplenum.strip()) 127 samplenum = int(samplenum.strip())
105 sample = int(sample, 16) 128 sample = int(sample, 16)
106 if detect_rise(last, sample, edclk):
107 edclk_ticks += 1
108 if detect_rise(last, sample, sc): 129 if detect_rise(last, sample, sc):
109 sc_ticks += 1 130 sc_ticks += 1
110 if not (last is False): 131 if not (last is False):
111 #detect falling edge of !HSYNC 132 #detect falling edge of !HSYNC
112 if detect_fall(last, sample, hsync): 133 if detect_fall(last, sample, hsync):
113 if readcounter: 134 if readcounter:
114 print readcounter, 'reads,', sillyread, 'redundant reads' 135 print readcounter, 'reads,', sillyread, 'redundant reads'
115 readcounter = sillyread = 0 136 readcounter = sillyread = 0
116 if not tick_start is False: 137 if not tick_start is False:
117 float(edclk_ticks)/((rate * (samplenum-tick_start)) / 1000.0)
118 print 'EDCLK:', edclk_ticks, ' ticks, {0}MHz'.format(float(edclk_ticks)/((rate * (samplenum-tick_start)) / 1000.0))
119 print 'SC:', sc_ticks, ' ticks, {0}MHz'.format(float(sc_ticks)/((rate * (samplenum-tick_start)) / 1000.0)) 138 print 'SC:', sc_ticks, ' ticks, {0}MHz'.format(float(sc_ticks)/((rate * (samplenum-tick_start)) / 1000.0))
120 tick_start = samplenum 139 tick_start = samplenum
121 edclk_ticks = sc_ticks = 0 140 edclk_ticks = sc_ticks = 0
122 print 'HSYNC Start' 141 print 'HSYNC Start @ {0} ns'.format((samplenum - triggerpos)*rate)
123 #detect rising edge of !HSYNC 142 #detect rising edge of !HSYNC
124 elif detect_rise(last, sample, hsync): 143 elif detect_rise(last, sample, hsync):
125 if not tick_start is False: 144 if not tick_start is False:
126 float(edclk_ticks)/((rate * (samplenum-tick_start)) / 1000.0) 145 float(edclk_ticks)/((rate * (samplenum-tick_start)) / 1000.0)
127 print 'EDCLK:', edclk_ticks, ' ticks, {0}MHz'.format(float(edclk_ticks)/((rate * (samplenum-tick_start)) / 1000.0)) 146 print 'EDCLK:', edclk_ticks, ' ticks, {0}MHz'.format(float(edclk_ticks)/((rate * (samplenum-tick_start)) / 1000.0))
128 print 'SC:', sc_ticks, ' ticks, {0}MHz'.format(float(sc_ticks)/((rate * (samplenum-tick_start)) / 1000.0)) 147 print 'SC:', sc_ticks, ' ticks, {0}MHz'.format(float(sc_ticks)/((rate * (samplenum-tick_start)) / 1000.0))
129 tick_start = samplenum 148 tick_start = samplenum
130 edclk_ticks = sc_ticks = 0 149 edclk_ticks = sc_ticks = 0
131 print 'HSYNC End' 150 print 'HSYNC End @ {0} ns'.format((samplenum - triggerpos)*rate)
151 if detect_fall(last, sample, vsync):
152 print 'VSYNC Start @ {0} ns'.format((samplenum - triggerpos)*rate)
153 elif detect_rise(last, sample, vsync):
154 print 'VSYNC End @ {0} ns'.format((samplenum - triggerpos)*rate)
155 if detect_fall(last, sample, ipl2):
156 print 'IPL2 Low @ {0} ns'.format((samplenum - triggerpos)*rate)
157 elif detect_rise(last, sample, ipl2):
158 print 'IPL2 High @ {0} ns'.format((samplenum - triggerpos)*rate)
132 if state == 'begin': 159 if state == 'begin':
133 #detect falling edge of !RAS 160 #detect falling edge of !RAS
134 if detect_fall(last, sample, ras): 161 if detect_fall(last, sample, ras):
135 state = 'ras' 162 state = 'ras'
136 row = get_addr(sample) 163 row = get_addr(sample)
137 mode = 'ram' if detect_high(sample, oedt) else 'read transfer' 164 mode = 'ram' if detect_high(sample, oedt) else 'read transfer'
138 elif detect_fall(last, sample, cas): 165 elif detect_fall(last, sample, cas) and detect_high(sample, oedt):
139 state = 'cas' 166 state = 'cas'
140 elif state == 'ras': 167 elif state == 'ras':
141 if detect_fall(last, sample, cas): 168 if detect_fall(last, sample, cas):
142 state = 'begin' 169 state = 'begin'
143 col = get_addr(sample) 170 col = get_addr(sample)