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comparison ym2612.c @ 1912:00fb99805445

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Skip invalid registers when dumping initial YM2612 state to VGM log
author Michael Pavone <pavone@retrodev.com>
date Sat, 28 Mar 2020 15:46:53 -0700
parents 508522f08e4d
children c3c62dbf1ceb
comparison
equal deleted inserted replaced
1911:f2ed8df7a002 1912:00fb99805445
782 void ym_vgm_log(ym2612_context *context, uint32_t master_clock, vgm_writer *vgm) 782 void ym_vgm_log(ym2612_context *context, uint32_t master_clock, vgm_writer *vgm)
783 { 783 {
784 vgm_ym2612_init(vgm, 6 * master_clock / context->clock_inc); 784 vgm_ym2612_init(vgm, 6 * master_clock / context->clock_inc);
785 context->vgm = vgm; 785 context->vgm = vgm;
786 for (uint8_t reg = YM_PART1_START; reg < YM_REG_END; reg++) { 786 for (uint8_t reg = YM_PART1_START; reg < YM_REG_END; reg++) {
787 if ((reg >= REG_DETUNE_MULT && (reg & 3) == 3) || (reg >= 0x2D && reg < REG_DETUNE_MULT) || reg == 0x23 || reg == 0x29) {
788 //skip invalid registers
789 continue;
790 }
787 vgm_ym2612_part1_write(context->vgm, context->current_cycle, reg, context->part1_regs[reg - YM_PART1_START]); 791 vgm_ym2612_part1_write(context->vgm, context->current_cycle, reg, context->part1_regs[reg - YM_PART1_START]);
788 } 792 }
789 793
790 for (uint8_t reg = YM_PART2_START; reg < YM_REG_END; reg++) { 794 for (uint8_t reg = YM_PART2_START; reg < YM_REG_END; reg++) {
795 if ((reg & 3) == 3 || (reg >= REG_FNUM_LOW_CH3 && reg < REG_ALG_FEEDBACK)) {
796 //skip invalid registers
797 continue;
798 }
791 vgm_ym2612_part2_write(context->vgm, context->current_cycle, reg, context->part2_regs[reg - YM_PART2_START]); 799 vgm_ym2612_part2_write(context->vgm, context->current_cycle, reg, context->part2_regs[reg - YM_PART2_START]);
792 } 800 }
793 } 801 }
794 802
795 void ym_data_write(ym2612_context * context, uint8_t value) 803 void ym_data_write(ym2612_context * context, uint8_t value)