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comparison vdp.h @ 1925:039553703c20

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Don't apply address and cd register changes to the 'live' registers until pending flag is cleared, but do preserve the upper address bits in the latch. Fixes regression in Overdrive 2 while preserving fix to Mona in 344 bytes
author Michael Pavone <pavone@retrodev.com>
date Mon, 13 Apr 2020 20:43:25 -0700
parents 2d462aa78349
children c3c62dbf1ceb
comparison
equal deleted inserted replaced
1924:81b059e3ded6 1925:039553703c20
172 uint32_t debug_fb_pitch[VDP_NUM_DEBUG_TYPES]; 172 uint32_t debug_fb_pitch[VDP_NUM_DEBUG_TYPES];
173 fifo_entry fifo[FIFO_SIZE]; 173 fifo_entry fifo[FIFO_SIZE];
174 int32_t fifo_write; 174 int32_t fifo_write;
175 int32_t fifo_read; 175 int32_t fifo_read;
176 uint32_t address; 176 uint32_t address;
177 uint32_t address_latch;
177 uint32_t serial_address; 178 uint32_t serial_address;
178 uint32_t colors[CRAM_SIZE*4]; 179 uint32_t colors[CRAM_SIZE*4];
179 uint32_t debugcolors[1 << (3 + 1 + 1 + 1)];//3 bits for source, 1 bit for priority, 1 bit for shadow, 1 bit for hilight 180 uint32_t debugcolors[1 << (3 + 1 + 1 + 1)];//3 bits for source, 1 bit for priority, 1 bit for shadow, 1 bit for hilight
180 uint16_t cram[CRAM_SIZE]; 181 uint16_t cram[CRAM_SIZE];
181 uint32_t frame; 182 uint32_t frame;
182 uint32_t vsram_size; 183 uint32_t vsram_size;
183 uint8_t cd; 184 uint8_t cd;
185 uint8_t cd_latch;
184 uint8_t flags; 186 uint8_t flags;
185 uint8_t regs[VDP_REGS]; 187 uint8_t regs[VDP_REGS];
186 //cycle count in MCLKs 188 //cycle count in MCLKs
187 uint32_t cycles; 189 uint32_t cycles;
188 uint32_t pending_vint_start; 190 uint32_t pending_vint_start;