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comparison m68k_to_x86.c @ 122:0a6da6c7c463

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Implemented ROL and ROR
author Mike Pavone <pavone@retrodev.com>
date Sat, 29 Dec 2012 20:33:39 -0800
parents f848aad2abef
children bd3858121ab0
comparison
equal deleted inserted replaced
121:f848aad2abef 122:0a6da6c7c463
1942 1942
1943 #define BIT_SUPERVISOR 5 1943 #define BIT_SUPERVISOR 5
1944 1944
1945 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) 1945 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
1946 { 1946 {
1947 uint8_t * end_off; 1947 uint8_t * end_off, *zero_off, *norm_off;
1948 map_native_address(opts->native_code_map, inst->address, dst); 1948 map_native_address(opts->native_code_map, inst->address, dst);
1949 dst = check_cycles_int(dst, inst->address); 1949 dst = check_cycles_int(dst, inst->address);
1950 if (inst->op == M68K_MOVE) { 1950 if (inst->op == M68K_MOVE) {
1951 return translate_m68k_move(dst, inst, opts); 1951 return translate_m68k_move(dst, inst, opts);
1952 } else if(inst->op == M68K_LEA) { 1952 } else if(inst->op == M68K_LEA) {
2336 } 2336 }
2337 if (inst->op == M68K_ANDI_SR) { 2337 if (inst->op == M68K_ANDI_SR) {
2338 dst = or_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B); 2338 dst = or_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
2339 } 2339 }
2340 break; 2340 break;
2341 /*case M68K_PEA: 2341 /*case M68K_RESET:*/
2342 case M68K_RESET:
2343 case M68K_ROL: 2342 case M68K_ROL:
2344 case M68K_ROR: 2343 case M68K_ROR:
2345 case M68K_ROXL: 2344 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
2345 if (inst->src.addr_mode == MODE_UNUSED) {
2346 dst = cycles(dst, BUS);
2347 //Memory rotate
2348 if (inst->op == M68K_ROL) {
2349 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size);
2350 } else {
2351 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size);
2352 }
2353 dst = setcc_r(dst, CC_C, FLAG_C);
2354 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
2355 dst = setcc_r(dst, CC_Z, FLAG_Z);
2356 dst = setcc_r(dst, CC_S, FLAG_N);
2357 dst = m68k_save_result(inst, dst, opts);
2358 } else {
2359 if (src_op.mode == MODE_IMMED) {
2360 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2);
2361 if (dst_op.mode == MODE_REG_DIRECT) {
2362 if (inst->op == M68K_ROL) {
2363 dst = rol_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
2364 } else {
2365 dst = ror_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
2366 }
2367 } else {
2368 if (inst->op == M68K_ROL) {
2369 dst = rol_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
2370 } else {
2371 dst = ror_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
2372 }
2373 }
2374 dst = setcc_r(dst, CC_C, FLAG_C);
2375 } else {
2376 if (src_op.mode == MODE_REG_DIRECT) {
2377 if (src_op.base != SCRATCH1) {
2378 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B);
2379 }
2380 } else {
2381 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
2382 }
2383 dst = and_ir(dst, 63, SCRATCH1, SZ_D);
2384 zero_off = dst+1;
2385 dst = jcc(dst, CC_NZ, dst+2);
2386 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
2387 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
2388 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B);
2389 norm_off = dst+1;
2390 dst = jcc(dst, CC_L, dst+2);
2391 if (dst_op.mode == MODE_REG_DIRECT) {
2392 if (inst->op == M68K_ROL) {
2393 dst = rol_ir(dst, 31, dst_op.base, inst->extra.size);
2394 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size);
2395 } else {
2396 dst = ror_ir(dst, 31, dst_op.base, inst->extra.size);
2397 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size);
2398 }
2399 } else {
2400 if (inst->op == M68K_ROL) {
2401 dst = rol_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
2402 dst = rol_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
2403 } else {
2404 dst = ror_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
2405 dst = ror_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
2406 }
2407 }
2408 dst = sub_ir(dst, 32, SCRATCH1, SZ_B);
2409 *norm_off = dst - (norm_off+1);
2410 if (dst_op.mode == MODE_REG_DIRECT) {
2411 if (inst->op == M68K_ROL) {
2412 dst = rol_clr(dst, dst_op.base, inst->extra.size);
2413 } else {
2414 dst = ror_clr(dst, dst_op.base, inst->extra.size);
2415 }
2416 } else {
2417 if (inst->op == M68K_ROL) {
2418 dst = rol_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
2419 } else {
2420 dst = ror_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
2421 }
2422 }
2423 dst = setcc_r(dst, CC_C, FLAG_C);
2424 end_off = dst + 1;
2425 dst = jmp(dst, dst+2);
2426 *zero_off = dst - (zero_off+1);
2427 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
2428 *end_off = dst - (end_off+1);
2429 }
2430 if (dst_op.mode == MODE_REG_DIRECT) {
2431 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
2432 } else {
2433 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
2434 }
2435 dst = setcc_r(dst, CC_Z, FLAG_Z);
2436 dst = setcc_r(dst, CC_S, FLAG_N);
2437 }
2438 break;
2439 /*case M68K_ROXL:
2346 case M68K_ROXR:*/ 2440 case M68K_ROXR:*/
2347 case M68K_RTE: 2441 case M68K_RTE:
2348 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); 2442 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
2349 dst = call(dst, (uint8_t *)m68k_read_long_scratch1); 2443 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
2350 dst = push_r(dst, SCRATCH1); 2444 dst = push_r(dst, SCRATCH1);
2364 dst = call(dst, (uint8_t *)m68k_native_addr_and_sync); 2458 dst = call(dst, (uint8_t *)m68k_native_addr_and_sync);
2365 dst = jmp_r(dst, SCRATCH1); 2459 dst = jmp_r(dst, SCRATCH1);
2366 break; 2460 break;
2367 /*case M68K_RTR: 2461 /*case M68K_RTR:
2368 case M68K_SBCD: 2462 case M68K_SBCD:
2369 case M68K_SCC:
2370 case M68K_STOP: 2463 case M68K_STOP:
2371 break;*/ 2464 break;*/
2372 case M68K_SUB: 2465 case M68K_SUB:
2373 dst = cycles(dst, BUS); 2466 dst = cycles(dst, BUS);
2374 if (src_op.mode == MODE_REG_DIRECT) { 2467 if (src_op.mode == MODE_REG_DIRECT) {