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comparison vdp.c @ 1175:0e0386fa795c

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Fix H40 VInt inconsistency
author Michael Pavone <pavone@retrodev.com>
date Tue, 17 Jan 2017 09:02:36 -0800
parents 500d8deea802
children 67e0462c30ce
comparison
equal deleted inserted replaced
1174:500d8deea802 1175:0e0386fa795c
2760 { 2760 {
2761 uint16_t vint_line = (context->regs[REG_MODE_2] & BIT_MODE_5) ? context->inactive_start : context->inactive_start + 1; 2761 uint16_t vint_line = (context->regs[REG_MODE_2] & BIT_MODE_5) ? context->inactive_start : context->inactive_start + 1;
2762 if (context->vcounter == vint_line) { 2762 if (context->vcounter == vint_line) {
2763 if (context->regs[REG_MODE_2] & BIT_MODE_5) { 2763 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
2764 if (context->regs[REG_MODE_4] & BIT_H40) { 2764 if (context->regs[REG_MODE_4] & BIT_H40) {
2765 if (context->hslot >= LINE_CHANGE_H40 && context->hslot <= VINT_SLOT_H40) { 2765 if (context->hslot >= LINE_CHANGE_H40 || context->hslot <= VINT_SLOT_H40) {
2766 uint32_t cycles = context->cycles; 2766 uint32_t cycles = context->cycles;
2767 if (context->hslot < 183) { 2767 if (context->hslot >= LINE_CHANGE_H40) {
2768 cycles += (183 - context->hslot) * MCLKS_SLOT_H40; 2768 if (context->hslot < 183) {
2769 cycles += (183 - context->hslot) * MCLKS_SLOT_H40;
2770 }
2771
2772 if (context->hslot < HSYNC_SLOT_H40) {
2773 cycles += (HSYNC_SLOT_H40 - (context->hslot >= 229 ? context->hslot : 229)) * MCLKS_SLOT_H40;
2774 }
2775 for (int slot = context->hslot <= HSYNC_SLOT_H40 ? HSYNC_SLOT_H40 : context->hslot; slot < HSYNC_END_H40; slot++ )
2776 {
2777 cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40];
2778 }
2779 cycles += (256 - (context->hslot > HSYNC_END_H40 ? context->hslot : HSYNC_END_H40)) * MCLKS_SLOT_H40;
2769 } 2780 }
2770 2781
2771 if (context->hslot < HSYNC_SLOT_H40) { 2782 cycles += (VINT_SLOT_H40 - (context->hslot >= LINE_CHANGE_H40 ? 0 : context->hslot)) * MCLKS_SLOT_H40;
2772 cycles += (HSYNC_SLOT_H40 - (context->hslot >= 229 ? context->hslot : 229)) * MCLKS_SLOT_H40;
2773 }
2774 for (int slot = context->hslot <= HSYNC_SLOT_H40 ? HSYNC_SLOT_H40 : context->hslot; slot < HSYNC_END_H40; slot++ )
2775 {
2776 cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40];
2777 }
2778 cycles += (VINT_SLOT_H40 - (context->hslot > HSYNC_END_H40 ? context->hslot : HSYNC_END_H40)) * MCLKS_SLOT_H40;
2779 return cycles; 2783 return cycles;
2780 } 2784 }
2781 } else { 2785 } else {
2782 if (context->hslot >= LINE_CHANGE_H32 || context->hslot <= VINT_SLOT_H32) { 2786 if (context->hslot >= LINE_CHANGE_H32 || context->hslot <= VINT_SLOT_H32) {
2783 if (context->hslot <= VINT_SLOT_H32) { 2787 if (context->hslot <= VINT_SLOT_H32) {
2799 } 2803 }
2800 } 2804 }
2801 int32_t cycles_to_vint = vdp_cycles_to_line(context, vint_line); 2805 int32_t cycles_to_vint = vdp_cycles_to_line(context, vint_line);
2802 if (context->regs[REG_MODE_2] & BIT_MODE_5) { 2806 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
2803 if (context->regs[REG_MODE_4] & BIT_H40) { 2807 if (context->regs[REG_MODE_4] & BIT_H40) {
2804 cycles_to_vint += MCLKS_LINE - (LINE_CHANGE_H40 + (256 - VINT_SLOT_H40)) * MCLKS_SLOT_H40; 2808 cycles_to_vint += MCLKS_LINE - (LINE_CHANGE_H40 - VINT_SLOT_H40) * MCLKS_SLOT_H40;
2805 } else { 2809 } else {
2806 cycles_to_vint += (VINT_SLOT_H32 + 256 - 233 + 148 - LINE_CHANGE_H32) * MCLKS_SLOT_H32; 2810 cycles_to_vint += (VINT_SLOT_H32 + 256 - 233 + 148 - LINE_CHANGE_H32) * MCLKS_SLOT_H32;
2807 } 2811 }
2808 } else { 2812 } else {
2809 cycles_to_vint += (256 - LINE_CHANGE_MODE4 + VINT_SLOT_MODE4) * MCLKS_SLOT_H32; 2813 cycles_to_vint += (256 - LINE_CHANGE_MODE4 + VINT_SLOT_MODE4) * MCLKS_SLOT_H32;