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comparison segacd.c @ 2144:10e4439d8f13

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Fix speed of CDC to PCM RAM DMA
author Michael Pavone <pavone@retrodev.com>
date Sat, 26 Mar 2022 00:54:47 -0700
parents b6338e18787e
children 2da377ea932f
comparison
equal deleted inserted replaced
2143:67f20f9188b0 2144:10e4439d8f13
739 cd->gate_array[reg] |= value & MASK_PRIORITY; 739 cd->gate_array[reg] |= value & MASK_PRIORITY;
740 cd->gate_array[reg] |= cd->main_has_word2m ? BIT_RET : BIT_DMNA; 740 cd->gate_array[reg] |= cd->main_has_word2m ? BIT_RET : BIT_DMNA;
741 } 741 }
742 break; 742 break;
743 } 743 }
744 case GA_CDC_CTRL: 744 case GA_CDC_CTRL: {
745 cdd_run(cd, m68k->current_cycle); 745 cdd_run(cd, m68k->current_cycle);
746 lc8951_ar_write(&cd->cdc, value); 746 lc8951_ar_write(&cd->cdc, value);
747 //cd->gate_array[reg] &= 0xC000; 747 //cd->gate_array[reg] &= 0xC000;
748 uint16_t old_dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
748 //apparently this clears EDT, should it also clear DSR? 749 //apparently this clears EDT, should it also clear DSR?
749 cd->gate_array[reg] = value & 0x0700; 750 cd->gate_array[reg] = value & 0x0700;
751 uint16_t dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
752 if (dest != old_dest) {
753 if (dest == DST_PCM_RAM) {
754 lc8951_set_dma_multiple(&cd->cdc, 21);
755 } else {
756 lc8951_set_dma_multiple(&cd->cdc, 6);
757 }
758 if ((old_dest < DST_MAIN_CPU || old_dest == 6) && dest >= DST_MAIN_CPU && dest != 6) {
759 lc8951_resume_transfer(&cd->cdc, m68k->current_cycle);
760 }
761 calculate_target_cycle(m68k);
762 }
750 cd->gate_array[GA_CDC_DMA_ADDR] = 0; 763 cd->gate_array[GA_CDC_DMA_ADDR] = 0;
751 cd->cdc_dst_low = 0; 764 cd->cdc_dst_low = 0;
752 break; 765 break;
766 }
753 case GA_CDC_REG_DATA: 767 case GA_CDC_REG_DATA:
754 cdd_run(cd, m68k->current_cycle); 768 cdd_run(cd, m68k->current_cycle);
755 printf("CDC write %X: %X @ %u\n", cd->cdc.ar, value, m68k->current_cycle); 769 printf("CDC write %X: %X @ %u\n", cd->cdc.ar, value, m68k->current_cycle);
756 lc8951_reg_write(&cd->cdc, value); 770 lc8951_reg_write(&cd->cdc, value);
757 calculate_target_cycle(m68k); 771 calculate_target_cycle(m68k);
1010 dma_addr++; 1024 dma_addr++;
1011 cd->cdc_dst_low = dma_addr & 7; 1025 cd->cdc_dst_low = dma_addr & 7;
1012 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3; 1026 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3;
1013 break; 1027 break;
1014 default: 1028 default:
1029 return 0;
1015 printf("Invalid CDC transfer destination %d\n", dest); 1030 printf("Invalid CDC transfer destination %d\n", dest);
1016 } 1031 }
1017 return 1; 1032 return 1;
1018 } 1033 }
1019 1034