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Make writes to control and data port block when DMA is in progress
author Mike Pavone <pavone@retrodev.com>
date Tue, 01 Jan 2013 07:06:57 -0800
parents e5487ef04619
children 6b593ea0ed90
comparison
equal deleted inserted replaced
148:4a400aec81bb 149:139e5dcd6aa3
182 void external_slot(vdp_context * context) 182 void external_slot(vdp_context * context)
183 { 183 {
184 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode 184 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode
185 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations 185 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations
186 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy 186 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy
187 if((context->regs[REG_MODE_2] & BIT_DMA_ENABLE) && (context->flags & FLAG_DMA_RUN)) { 187 if(context->flags & FLAG_DMA_RUN) {
188 uint16_t dma_len; 188 uint16_t dma_len;
189 switch(context->regs[REG_DMASRC_H] & 0xC0) 189 switch(context->regs[REG_DMASRC_H] & 0xC0)
190 { 190 {
191 //68K -> VDP 191 //68K -> VDP
192 case 0: 192 case 0:
1020 } 1020 }
1021 1021
1022 int vdp_control_port_write(vdp_context * context, uint16_t value) 1022 int vdp_control_port_write(vdp_context * context, uint16_t value)
1023 { 1023 {
1024 //printf("control port write: %X\n", value); 1024 //printf("control port write: %X\n", value);
1025 if (context->flags & FLAG_DMA_RUN) {
1026 return -1;
1027 }
1025 if (context->flags & FLAG_PENDING) { 1028 if (context->flags & FLAG_PENDING) {
1026 context->address = (context->address & 0x3FFF) | (value << 14); 1029 context->address = (context->address & 0x3FFF) | (value << 14);
1027 context->cd = (context->cd & 0x3) | ((value >> 2) & 0x3C); 1030 context->cd = (context->cd & 0x3) | ((value >> 2) & 0x3C);
1028 context->flags &= ~FLAG_PENDING; 1031 context->flags &= ~FLAG_PENDING;
1029 //printf("New Address: %X, New CD: %X\n", context->address, context->cd); 1032 //printf("New Address: %X, New CD: %X\n", context->address, context->cd);
1055 } 1058 }
1056 } 1059 }
1057 return 0; 1060 return 0;
1058 } 1061 }
1059 1062
1060 void vdp_data_port_write(vdp_context * context, uint16_t value) 1063 int vdp_data_port_write(vdp_context * context, uint16_t value)
1061 { 1064 {
1062 //printf("data port write: %X\n", value); 1065 //printf("data port write: %X\n", value);
1066 if (context->flags & FLAG_DMA_RUN) {
1067 return -1;
1068 }
1069 if (!(context->cd & 1)) {
1070 //ignore writes when cd is configured for read
1071 return 0;
1072 }
1063 context->flags &= ~FLAG_PENDING; 1073 context->flags &= ~FLAG_PENDING;
1064 /*if (context->fifo_cur == context->fifo_end) { 1074 /*if (context->fifo_cur == context->fifo_end) {
1065 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles); 1075 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles);
1066 }*/ 1076 }*/
1067 while (context->fifo_cur == context->fifo_end) { 1077 while (context->fifo_cur == context->fifo_end) {
1072 context->fifo_cur->value = value; 1082 context->fifo_cur->value = value;
1073 context->fifo_cur->cd = context->cd; 1083 context->fifo_cur->cd = context->cd;
1074 context->fifo_cur->partial = 0; 1084 context->fifo_cur->partial = 0;
1075 context->fifo_cur++; 1085 context->fifo_cur++;
1076 context->address += context->regs[REG_AUTOINC]; 1086 context->address += context->regs[REG_AUTOINC];
1087 return 0;
1077 } 1088 }
1078 1089
1079 uint16_t vdp_control_port_read(vdp_context * context) 1090 uint16_t vdp_control_port_read(vdp_context * context)
1080 { 1091 {
1081 context->flags &= ~FLAG_PENDING; 1092 context->flags &= ~FLAG_PENDING;
1084 value |= 0x200; 1095 value |= 0x200;
1085 } 1096 }
1086 if (context->fifo_cur == context->fifo_end) { 1097 if (context->fifo_cur == context->fifo_end) {
1087 value |= 0x100; 1098 value |= 0x100;
1088 } 1099 }
1089 if ((context->regs[REG_MODE_2] & BIT_DMA_ENABLE) && (context->flags & FLAG_DMA_RUN)) { 1100 if (context->flags & FLAG_DMA_RUN) {
1090 value |= 0x2; 1101 value |= 0x2;
1091 } 1102 }
1092 uint32_t line= context->cycles / MCLKS_LINE; 1103 uint32_t line= context->cycles / MCLKS_LINE;
1093 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE)) { 1104 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE)) {
1094 value |= 0x8; 1105 value |= 0x8;