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comparison vdp.c @ 1172:14eb8ff4fb03

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Added synthetic test for tracking down interrupt timing issues
author Michael Pavone <pavone@retrodev.com>
date Mon, 16 Jan 2017 21:38:49 -0800
parents 43fa92976ff2
children d0f67c59b756
comparison
equal deleted inserted replaced
1171:43fa92976ff2 1172:14eb8ff4fb03
52 #define BORDER_BOT_V24_PAL 48 52 #define BORDER_BOT_V24_PAL 48
53 #define BORDER_BOT_V28_PAL 32 53 #define BORDER_BOT_V28_PAL 32
54 #define BORDER_BOT_V30_PAL 24 54 #define BORDER_BOT_V30_PAL 24
55 55
56 #define INVALID_LINE 0x200 56 #define INVALID_LINE 0x200
57 #define TIMING_DEBUG
57 58
58 static int32_t color_map[1 << 12]; 59 static int32_t color_map[1 << 12];
59 static uint16_t mode4_address_map[0x4000]; 60 static uint16_t mode4_address_map[0x4000];
60 static uint32_t planar_to_chunky[256]; 61 static uint32_t planar_to_chunky[256];
61 static uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255}; 62 static uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255};
2758 if (context->vcounter == vint_line) { 2759 if (context->vcounter == vint_line) {
2759 if (context->regs[REG_MODE_2] & BIT_MODE_5) { 2760 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
2760 if (context->regs[REG_MODE_4] & BIT_H40) { 2761 if (context->regs[REG_MODE_4] & BIT_H40) {
2761 if (context->hslot >= LINE_CHANGE_H40 && context->hslot <= VINT_SLOT_H40) { 2762 if (context->hslot >= LINE_CHANGE_H40 && context->hslot <= VINT_SLOT_H40) {
2762 uint32_t cycles = context->cycles; 2763 uint32_t cycles = context->cycles;
2763 if (context->hslot < 182) { 2764 if (context->hslot < 183) {
2764 cycles += (182 - context->hslot) * MCLKS_SLOT_H40; 2765 cycles += (183 - context->hslot) * MCLKS_SLOT_H40;
2765 } 2766 }
2766 2767
2767 if (context->hslot < 229) { 2768 if (context->hslot < HSYNC_SLOT_H40) {
2768 cycles += h40_hsync_cycles[0]; 2769 cycles += (HSYNC_SLOT_H40 - (context->hslot >= 229 ? context->hslot : 229)) * MCLKS_SLOT_H40;
2769 } 2770 }
2770 for (int slot = context->hslot <= 229 ? 229 : context->hslot; slot < HSYNC_END_H40; slot++ ) 2771 for (int slot = context->hslot <= HSYNC_SLOT_H40 ? HSYNC_SLOT_H40 : context->hslot; slot < HSYNC_END_H40; slot++ )
2771 { 2772 {
2772 cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40]; 2773 cycles += h40_hsync_cycles[slot - HSYNC_SLOT_H40];
2773 } 2774 }
2774 cycles += (VINT_SLOT_H40 - (context->hslot > HSYNC_SLOT_H40 ? context->hslot : HSYNC_SLOT_H40)) * MCLKS_SLOT_H40; 2775 cycles += (VINT_SLOT_H40 - (context->hslot > HSYNC_END_H40 ? context->hslot : HSYNC_END_H40)) * MCLKS_SLOT_H40;
2775 return cycles; 2776 return cycles;
2776 } 2777 }
2777 } else { 2778 } else {
2778 if (context->hslot >= LINE_CHANGE_H32 && context->hslot <= VINT_SLOT_H32) { 2779 if (context->hslot >= LINE_CHANGE_H32 && context->hslot <= VINT_SLOT_H32) {
2779 if (context->hslot < 233) { 2780 if (context->hslot < 233) {