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comparison m68k_core_x86.c @ 2101:17ecd28ddc8a

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Fix handling of address error for 32-bit accesses
author Michael Pavone <pavone@retrodev.com>
date Wed, 09 Feb 2022 23:39:33 -0800
parents 973a39d93d7b
children 522d04e2adcd
comparison
equal deleted inserted replaced
2100:539450d905b3 2101:17ecd28ddc8a
2736 opts->read_8 = gen_mem_fun(&opts->gen, memmap, num_chunks, READ_8, NULL); 2736 opts->read_8 = gen_mem_fun(&opts->gen, memmap, num_chunks, READ_8, NULL);
2737 opts->write_16 = gen_mem_fun(&opts->gen, memmap, num_chunks, WRITE_16, NULL); 2737 opts->write_16 = gen_mem_fun(&opts->gen, memmap, num_chunks, WRITE_16, NULL);
2738 opts->write_8 = gen_mem_fun(&opts->gen, memmap, num_chunks, WRITE_8, NULL); 2738 opts->write_8 = gen_mem_fun(&opts->gen, memmap, num_chunks, WRITE_8, NULL);
2739 2739
2740 opts->read_32 = code->cur; 2740 opts->read_32 = code->cur;
2741 if (opts->gen.align_error_mask) {
2742 test_ir(code, opts->gen.align_error_mask, opts->gen.scratch1, SZ_D);
2743 jcc(code, CC_NZ, opts->gen.handle_align_error_read);
2744 }
2741 push_r(code, opts->gen.scratch1); 2745 push_r(code, opts->gen.scratch1);
2742 call(code, opts->read_16); 2746 call(code, opts->read_16);
2743 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_W); 2747 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_W);
2744 pop_r(code, opts->gen.scratch1); 2748 pop_r(code, opts->gen.scratch1);
2745 push_r(code, opts->gen.scratch2); 2749 push_r(code, opts->gen.scratch2);
2750 shl_ir(code, 16, opts->gen.scratch2, SZ_D); 2754 shl_ir(code, 16, opts->gen.scratch2, SZ_D);
2751 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_D); 2755 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_D);
2752 retn(code); 2756 retn(code);
2753 2757
2754 opts->write_32_lowfirst = code->cur; 2758 opts->write_32_lowfirst = code->cur;
2759 if (opts->gen.align_error_mask) {
2760 test_ir(code, opts->gen.align_error_mask, opts->gen.scratch2, SZ_D);
2761 jcc(code, CC_NZ, opts->gen.handle_align_error_write);
2762 }
2755 push_r(code, opts->gen.scratch2); 2763 push_r(code, opts->gen.scratch2);
2756 push_r(code, opts->gen.scratch1); 2764 push_r(code, opts->gen.scratch1);
2757 add_ir(code, 2, opts->gen.scratch2, SZ_D); 2765 add_ir(code, 2, opts->gen.scratch2, SZ_D);
2758 call(code, opts->write_16); 2766 call(code, opts->write_16);
2759 pop_r(code, opts->gen.scratch1); 2767 pop_r(code, opts->gen.scratch1);
2760 pop_r(code, opts->gen.scratch2); 2768 pop_r(code, opts->gen.scratch2);
2761 shr_ir(code, 16, opts->gen.scratch1, SZ_D); 2769 shr_ir(code, 16, opts->gen.scratch1, SZ_D);
2762 jmp(code, opts->write_16); 2770 jmp(code, opts->write_16);
2763 2771
2764 opts->write_32_highfirst = code->cur; 2772 opts->write_32_highfirst = code->cur;
2773 if (opts->gen.align_error_mask) {
2774 test_ir(code, opts->gen.align_error_mask, opts->gen.scratch2, SZ_D);
2775 jcc(code, CC_NZ, opts->gen.handle_align_error_write);
2776 }
2765 push_r(code, opts->gen.scratch1); 2777 push_r(code, opts->gen.scratch1);
2766 push_r(code, opts->gen.scratch2); 2778 push_r(code, opts->gen.scratch2);
2767 shr_ir(code, 16, opts->gen.scratch1, SZ_D); 2779 shr_ir(code, 16, opts->gen.scratch1, SZ_D);
2768 call(code, opts->write_16); 2780 call(code, opts->write_16);
2769 pop_r(code, opts->gen.scratch2); 2781 pop_r(code, opts->gen.scratch2);