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comparison vdp.h @ 2257:1e626d0ecf9c
WIP SG-1000/TMS9918A mode support
author | Michael Pavone <pavone@retrodev.com> |
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date | Sat, 17 Dec 2022 23:32:34 -0800 |
parents | 0d1d5dccdd28 |
children | 83f5529086c5 |
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2256:cbe1ba70c247 | 2257:1e626d0ecf9c |
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33 #define SAT_CACHE_SIZE (MAX_SPRITES_FRAME * 4) | 33 #define SAT_CACHE_SIZE (MAX_SPRITES_FRAME * 4) |
34 | 34 |
35 #define FBUF_SHADOW 0x0001 | 35 #define FBUF_SHADOW 0x0001 |
36 #define FBUF_HILIGHT 0x0010 | 36 #define FBUF_HILIGHT 0x0010 |
37 #define FBUF_MODE4 0x0100 | 37 #define FBUF_MODE4 0x0100 |
38 #define FBUF_MASK (FBUF_SHADOW|FBUF_HILIGHT|FBUF_MODE4) | |
39 #define FBUF_TMS (FBUF_MODE4 | FBUF_SHADOW) | |
38 #define DBG_SHADOW 0x10 | 40 #define DBG_SHADOW 0x10 |
39 #define DBG_HILIGHT 0x20 | 41 #define DBG_HILIGHT 0x20 |
40 #define DBG_PRIORITY 0x8 | 42 #define DBG_PRIORITY 0x8 |
41 #define DBG_SRC_MASK 0x7 | 43 #define DBG_SRC_MASK 0x7 |
42 #define DBG_SRC_A 0x1 | 44 #define DBG_SRC_A 0x1 |
92 REG_DMASRC_L, | 94 REG_DMASRC_L, |
93 REG_DMASRC_M, | 95 REG_DMASRC_M, |
94 REG_DMASRC_H, | 96 REG_DMASRC_H, |
95 REG_KMOD_CTRL=29, | 97 REG_KMOD_CTRL=29, |
96 REG_KMOD_MSG, | 98 REG_KMOD_MSG, |
97 REG_KMOD_TIMER | 99 REG_KMOD_TIMER, |
100 REG_COLOR_TABLE=REG_WINDOW, | |
101 REG_PATTERN_GEN=REG_SCROLL_B | |
98 }; | 102 }; |
99 | 103 |
100 //Mode reg 1 | 104 //Mode reg 1 |
101 #define BIT_VSCRL_LOCK 0x80 | 105 #define BIT_VSCRL_LOCK 0x80 |
102 #define BIT_HSCRL_LOCK 0x40 | 106 #define BIT_HSCRL_LOCK 0x40 |
104 #define BIT_HINT_EN 0x10 | 108 #define BIT_HINT_EN 0x10 |
105 #define BIT_SPRITE_8PX 0x08 | 109 #define BIT_SPRITE_8PX 0x08 |
106 #define BIT_PAL_SEL 0x04 | 110 #define BIT_PAL_SEL 0x04 |
107 #define BIT_MODE_4 BIT_PAL_SEL | 111 #define BIT_MODE_4 BIT_PAL_SEL |
108 #define BIT_HVC_LATCH 0x02 | 112 #define BIT_HVC_LATCH 0x02 |
113 #define BIT_M3 BIT_HVC_LATCH | |
109 #define BIT_DISP_DIS 0x01 | 114 #define BIT_DISP_DIS 0x01 |
110 | 115 |
111 //Mode reg 2 | 116 //Mode reg 2 |
112 #define BIT_128K_VRAM 0x80 | 117 #define BIT_128K_VRAM 0x80 |
118 #define BIT_16K_VRAM BIT_128K_VRAM | |
113 #define BIT_DISP_EN 0x40 | 119 #define BIT_DISP_EN 0x40 |
114 #define BIT_VINT_EN 0x20 | 120 #define BIT_VINT_EN 0x20 |
115 #define BIT_DMA_ENABLE 0x10 | 121 #define BIT_DMA_ENABLE 0x10 |
122 #define BIT_M1 BIT_DMA_ENABLE | |
116 #define BIT_PAL 0x08 | 123 #define BIT_PAL 0x08 |
124 #define BIT_M2 BIT_PAL | |
117 #define BIT_MODE_5 0x04 | 125 #define BIT_MODE_5 0x04 |
118 #define BIT_SPRITE_SZ 0x02 | 126 #define BIT_SPRITE_SZ 0x02 |
119 #define BIT_SPRITE_ZM 0x01 | 127 #define BIT_SPRITE_ZM 0x01 |
120 | 128 |
121 //Mode reg 3 | 129 //Mode reg 3 |