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comparison vdp.c @ 1956:275f1c4bdb25

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Netplay protocol size optimization
author Michael Pavone <pavone@retrodev.com>
date Fri, 01 May 2020 23:39:45 -0700
parents c3c62dbf1ceb
children ba06346611a1
comparison
equal deleted inserted replaced
1955:1c7af12efe8b 1956:275f1c4bdb25
937 val = (context->cram[address] & 0xFF00) | start->value; 937 val = (context->cram[address] & 0xFF00) | start->value;
938 } 938 }
939 } else { 939 } else {
940 val = start->partial ? context->fifo[context->fifo_write].value : start->value; 940 val = start->partial ? context->fifo[context->fifo_write].value : start->value;
941 } 941 }
942 uint8_t buffer[3] = {start->address, val >> 8, val}; 942 uint8_t buffer[3] = {start->address & 127, val >> 8, val};
943 event_log(EVENT_CRAM, context->cycles, sizeof(buffer), buffer); 943 event_log(EVENT_VDP_INTRAM, context->cycles, sizeof(buffer), buffer);
944 write_cram(context, start->address, val); 944 write_cram(context, start->address, val);
945 break; 945 break;
946 } 946 }
947 case VSRAM_WRITE: 947 case VSRAM_WRITE:
948 if (((start->address/2) & 63) < context->vsram_size) { 948 if (((start->address/2) & 63) < context->vsram_size) {
956 context->vsram[(start->address/2) & 63] |= start->value; 956 context->vsram[(start->address/2) & 63] |= start->value;
957 } 957 }
958 } else { 958 } else {
959 context->vsram[(start->address/2) & 63] = start->partial ? context->fifo[context->fifo_write].value : start->value; 959 context->vsram[(start->address/2) & 63] = start->partial ? context->fifo[context->fifo_write].value : start->value;
960 } 960 }
961 uint8_t buffer[3] = {(start->address/2) & 63, context->vsram[(start->address/2) & 63] >> 8, context->vsram[(start->address/2) & 63]}; 961 uint8_t buffer[3] = {((start->address/2) & 63) + 128, context->vsram[(start->address/2) & 63] >> 8, context->vsram[(start->address/2) & 63]};
962 event_log(EVENT_VSRAM, context->cycles, sizeof(buffer), buffer); 962 event_log(EVENT_VDP_INTRAM, context->cycles, sizeof(buffer), buffer);
963 } 963 }
964 964
965 break; 965 break;
966 } 966 }
967 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1); 967 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1);
4588 break; 4588 break;
4589 case EVENT_VRAM_WORD_DELTA: 4589 case EVENT_VRAM_WORD_DELTA:
4590 address = reader->last_word_address + load_int8(buffer); 4590 address = reader->last_word_address + load_int8(buffer);
4591 break; 4591 break;
4592 case EVENT_VDP_REG: 4592 case EVENT_VDP_REG:
4593 case EVENT_CRAM: 4593 case EVENT_VDP_INTRAM:
4594 case EVENT_VSRAM:
4595 address = load_int8(buffer); 4594 address = load_int8(buffer);
4596 break; 4595 break;
4597 } 4596 }
4598 4597
4599 switch (event) 4598 switch (event)
4628 reader->last_word_address = address; 4627 reader->last_word_address = address;
4629 vdp_check_update_sat(context, address, value); 4628 vdp_check_update_sat(context, address, value);
4630 write_vram_word(context, address, value); 4629 write_vram_word(context, address, value);
4631 break; 4630 break;
4632 } 4631 }
4633 case EVENT_CRAM: 4632 case EVENT_VDP_INTRAM:
4634 write_cram(context, address, load_int16(buffer)); 4633 if (address < 128) {
4634 write_cram(context, address, load_int16(buffer));
4635 } else {
4636 context->vsram[address&63] = load_int16(buffer);
4637 }
4635 break; 4638 break;
4636 case EVENT_VSRAM: 4639 }
4637 context->vsram[address] = load_int16(buffer); 4640 }
4638 break;
4639 }
4640 }