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comparison cpu_dsl.py @ 1615:28f80d1b343e

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Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
author Michael Pavone <pavone@retrodev.com>
date Mon, 24 Sep 2018 19:09:16 -0700
parents c9639139aedf
children 8c78543c4783
comparison
equal deleted inserted replaced
1614:c9639139aedf 1615:28f80d1b343e
680 self.regs[name] = size 680 self.regs[name] = size
681 681
682 def addRegArray(self, name, size, regs): 682 def addRegArray(self, name, size, regs):
683 self.regArrays[name] = (size, regs) 683 self.regArrays[name] = (size, regs)
684 idx = 0 684 idx = 0
685 for reg in regs: 685 if not type(regs) is int:
686 self.regs[reg] = size 686 for reg in regs:
687 self.regToArray[reg] = (name, idx) 687 self.regs[reg] = size
688 idx += 1 688 self.regToArray[reg] = (name, idx)
689 idx += 1
689 690
690 def isReg(self, name): 691 def isReg(self, name):
691 return name in self.regs 692 return name in self.regs
692 693
693 def isRegArray(self, name): 694 def isRegArray(self, name):
701 702
702 def arrayMemberIndex(self, name): 703 def arrayMemberIndex(self, name):
703 return self.regToArray[name][1] 704 return self.regToArray[name][1]
704 705
705 def arrayMemberName(self, array, index): 706 def arrayMemberName(self, array, index):
706 if type(index) is int: 707 if type(index) is int and not type(self.regArrays[array][1]) is int:
707 return self.regArrays[array][1][index] 708 return self.regArrays[array][1][index]
708 else: 709 else:
709 return None 710 return None
711
712 def isNamedArray(self, array):
713 return array in self.regArrays and type(self.regArrays[array][1]) is int
710 714
711 def processLine(self, parts): 715 def processLine(self, parts):
712 if len(parts) > 2: 716 if len(parts) == 3:
717 self.addRegArray(parts[0], int(parts[1]), int(parts[2]))
718 elif len(parts) > 2:
713 self.addRegArray(parts[0], int(parts[1]), parts[2:]) 719 self.addRegArray(parts[0], int(parts[1]), parts[2:])
714 else: 720 else:
715 self.addReg(parts[0], int(parts[1])) 721 self.addReg(parts[0], int(parts[1]))
716 return self 722 return self
717 723
981 if not type(end) is int and self.regs.isRegArrayMember(end): 987 if not type(end) is int and self.regs.isRegArrayMember(end):
982 arrayName = self.regs.arrayMemberParent(end) 988 arrayName = self.regs.arrayMemberParent(end)
983 end = self.regs.arrayMemberIndex(end) 989 end = self.regs.arrayMemberIndex(end)
984 if arrayName != begin: 990 if arrayName != begin:
985 end = 'context->{0}[{1}]'.format(arrayName, end) 991 end = 'context->{0}[{1}]'.format(arrayName, end)
986 regName = self.regs.arrayMemberName(begin, end) 992 if self.regs.isNamedArray(begin):
993 regName = self.regs.arrayMemberName(begin, end)
994 else:
995 regName = '{0}.{1}'.format(begin, end)
987 ret = 'context->{0}[{1}]'.format(begin, end) 996 ret = 'context->{0}[{1}]'.format(begin, end)
988 else: 997 else:
989 regName = name 998 regName = name
990 if self.regs.isRegArrayMember(name): 999 if self.regs.isRegArrayMember(name):
991 arr,idx = self.regs.regToArray[name] 1000 arr,idx = self.regs.regToArray[name]