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comparison m68k_to_x86.c @ 64:2b1a65f4b85d

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Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
author Mike Pavone <pavone@retrodev.com>
date Wed, 19 Dec 2012 21:25:39 -0800
parents 918468c623e9
children 7a22a0e6c004
comparison
equal deleted inserted replaced
63:a6dd5b7a971b 64:2b1a65f4b85d
40 void m68k_start_context(uint8_t * addr, m68k_context * context); 40 void m68k_start_context(uint8_t * addr, m68k_context * context);
41 41
42 uint8_t * cycles(uint8_t * dst, uint32_t num) 42 uint8_t * cycles(uint8_t * dst, uint32_t num)
43 { 43 {
44 dst = add_ir(dst, num, CYCLES, SZ_D); 44 dst = add_ir(dst, num, CYCLES, SZ_D);
45 }
46
47 uint8_t * check_cycles(uint8_t * dst)
48 {
49 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D);
50 dst = jcc(dst, CC_G, dst+7);
51 dst = call(dst, (char *)handle_cycle_limit);
52 } 45 }
53 46
54 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts) 47 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts)
55 { 48 {
56 if (op->addr_mode == MODE_REG) { 49 if (op->addr_mode == MODE_REG) {
117 if (opts->aregs[inst->src.params.regs.pri] >= 0) { 110 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
118 out = sub_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D); 111 out = sub_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
119 } else { 112 } else {
120 out = sub_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D); 113 out = sub_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
121 } 114 }
122 out = check_cycles(out);
123 case MODE_AREG_INDIRECT: 115 case MODE_AREG_INDIRECT:
124 case MODE_AREG_POSTINC: 116 case MODE_AREG_POSTINC:
125 if (opts->aregs[inst->src.params.regs.pri] >= 0) { 117 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
126 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); 118 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
127 } else { 119 } else {
175 ea->base = SCRATCH1; 167 ea->base = SCRATCH1;
176 break; 168 break;
177 case MODE_IMMEDIATE: 169 case MODE_IMMEDIATE:
178 case MODE_IMMEDIATE_WORD: 170 case MODE_IMMEDIATE_WORD:
179 if (inst->variant != VAR_QUICK) { 171 if (inst->variant != VAR_QUICK) {
180 if (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) { 172 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS);
181 out = cycles(out, BUS);
182 out = check_cycles(out);
183 }
184 out = cycles(out, BUS);
185 out = check_cycles(out);
186 } 173 }
187 ea->mode = MODE_IMMED; 174 ea->mode = MODE_IMMED;
188 ea->disp = inst->src.params.immed; 175 ea->disp = inst->src.params.immed;
189 break; 176 break;
190 default: 177 default:
505 exit(1); 492 exit(1);
506 } 493 }
507 494
508 //add cycles for prefetch 495 //add cycles for prefetch
509 dst = cycles(dst, BUS); 496 dst = cycles(dst, BUS);
510 dst = check_cycles(dst);
511 return dst; 497 return dst;
512 } 498 }
513 499
514 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) 500 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
515 { 501 {
517 dst = mov_ir(dst, 0, FLAG_V, SZ_B); 503 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
518 dst = mov_ir(dst, 0, FLAG_C, SZ_B); 504 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
519 dst = mov_ir(dst, 1, FLAG_Z, SZ_B); 505 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
520 uint8_t reg = native_reg(&(inst->dst), opts); 506 uint8_t reg = native_reg(&(inst->dst), opts);
521 if (reg >= 0) { 507 if (reg >= 0) {
522 dst = xor_rr(dst, reg, reg, inst->extra.size); 508 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4));
523 return check_cycles(dst); 509 return xor_rr(dst, reg, reg, inst->extra.size);
524 } 510 }
525 int32_t dec_amount,inc_amount; 511 int32_t dec_amount,inc_amount;
526 switch (inst->dst.addr_mode) 512 switch (inst->dst.addr_mode)
527 { 513 {
528 case MODE_REG: 514 case MODE_REG:
529 case MODE_AREG: 515 case MODE_AREG:
530 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4)); 516 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4));
531 dst = mov_irdisp8(dst, 0, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size); 517 dst = mov_irdisp8(dst, 0, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size);
532 dst = check_cycles(dst);
533 break; 518 break;
534 case MODE_AREG_PREDEC: 519 case MODE_AREG_PREDEC:
535 dst = cycles(dst, PREDEC_PENALTY); 520 dst = cycles(dst, PREDEC_PENALTY);
536 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1); 521 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
537 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { 522 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
541 } 526 }
542 case MODE_AREG_INDIRECT: 527 case MODE_AREG_INDIRECT:
543 case MODE_AREG_POSTINC: 528 case MODE_AREG_POSTINC:
544 //add cycles for prefetch and wasted read 529 //add cycles for prefetch and wasted read
545 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 12 : 8)); 530 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 12 : 8));
546 dst = check_cycles(dst);
547 if (opts->aregs[inst->dst.params.regs.pri] >= 0) { 531 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
548 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D); 532 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
549 } else { 533 } else {
550 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D); 534 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
551 } 535 }
594 } else { 578 } else {
595 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); 579 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
596 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); 580 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
597 } 581 }
598 } 582 }
599 dst = check_cycles(dst);
600 break; 583 break;
601 case MODE_ABSOLUTE: 584 case MODE_ABSOLUTE:
602 dst = cycles(dst, BUS);
603 dst = check_cycles(dst);
604 case MODE_ABSOLUTE_SHORT: 585 case MODE_ABSOLUTE_SHORT:
605 dst = cycles(dst, BUS); 586 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2);
606 dst = check_cycles(dst);
607 dst = cycles(dst, BUS);
608 if (dst_reg >= 0) { 587 if (dst_reg >= 0) {
609 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D); 588 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D);
610 } else { 589 } else {
611 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D); 590 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
612 } 591 }
613 dst = check_cycles(dst);
614 break; 592 break;
615 } 593 }
616 return dst; 594 return dst;
617 } 595 }
618 596
716 if (opts->aregs[inst->src.params.regs.pri] >= 0) { 694 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
717 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D); 695 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
718 } else { 696 } else {
719 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D); 697 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
720 } 698 }
721 dst = check_cycles(dst);
722 dst = call(dst, (uint8_t *)m68k_native_addr); 699 dst = call(dst, (uint8_t *)m68k_native_addr);
723 //TODO: Finish me 700 //TODO: Finish me
724 //TODO: Fix timing 701 //TODO: Fix timing
725 break; 702 break;
726 case MODE_ABSOLUTE: 703 case MODE_ABSOLUTE:
727 case MODE_ABSOLUTE_SHORT: 704 case MODE_ABSOLUTE_SHORT:
728 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10); 705 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
729 dst = check_cycles(dst);
730 dest_addr = get_native_address(opts->native_code_map, inst->src.params.immed); 706 dest_addr = get_native_address(opts->native_code_map, inst->src.params.immed);
731 if (!dest_addr) { 707 if (!dest_addr) {
732 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1); 708 opts->deferred = defer_address(opts->deferred, inst->src.params.immed, dst + 1);
733 //dummy address to be replaced later, make sure it generates a 4-byte displacement 709 //dummy address to be replaced later, make sure it generates a 4-byte displacement
734 dest_addr = dst + 256; 710 dest_addr = dst + 256;
754 730
755 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) 731 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
756 { 732 {
757 //best case duration 733 //best case duration
758 dst = cycles(dst, 10); 734 dst = cycles(dst, 10);
759 dst = check_cycles(dst);
760 uint8_t * skip_loc = NULL; 735 uint8_t * skip_loc = NULL;
761 //TODO: Check if COND_TRUE technically valid here even though 736 //TODO: Check if COND_TRUE technically valid here even though
762 //it's basically a slow NOP 737 //it's basically a slow NOP
763 if (inst->extra.cond != COND_FALSE) { 738 if (inst->extra.cond != COND_FALSE) {
764 uint8_t cond = CC_NZ; 739 uint8_t cond = CC_NZ;
829 *skip_loc = dst - (skip_loc+1); 804 *skip_loc = dst - (skip_loc+1);
830 dst = cycles(dst, 2); 805 dst = cycles(dst, 2);
831 } else { 806 } else {
832 dst = cycles(dst, 4); 807 dst = cycles(dst, 4);
833 } 808 }
834 dst = check_cycles(dst);
835 return dst; 809 return dst;
836 } 810 }
837 811
838 typedef uint8_t * (*shift_ir_t)(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size); 812 typedef uint8_t * (*shift_ir_t)(uint8_t * out, uint8_t val, uint8_t dst, uint8_t size);
839 typedef uint8_t * (*shift_irdisp8_t)(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size); 813 typedef uint8_t * (*shift_irdisp8_t)(uint8_t * out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size);
843 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea *src_op, x86_ea * dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8) 817 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea *src_op, x86_ea * dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8)
844 { 818 {
845 uint8_t * end_off = NULL; 819 uint8_t * end_off = NULL;
846 if (inst->src.addr_mode == MODE_UNUSED) { 820 if (inst->src.addr_mode == MODE_UNUSED) {
847 dst = cycles(dst, BUS); 821 dst = cycles(dst, BUS);
848 dst = check_cycles(dst);
849 //Memory shift 822 //Memory shift
850 dst = shift_ir(dst, 1, dst_op->base, SZ_W); 823 dst = shift_ir(dst, 1, dst_op->base, SZ_W);
851 } else { 824 } else {
852 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6); 825 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6);
853 dst = check_cycles(dst);
854 if (src_op->mode == MODE_IMMED) { 826 if (src_op->mode == MODE_IMMED) {
855 if (dst_op->mode == MODE_REG_DIRECT) { 827 if (dst_op->mode == MODE_REG_DIRECT) {
856 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size); 828 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size);
857 } else { 829 } else {
858 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size); 830 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size);
931 dst = mov_ir(dst, 0, FLAG_V, SZ_B); 903 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
932 //set X flag to same as C flag 904 //set X flag to same as C flag
933 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); 905 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
934 if (inst->src.addr_mode == MODE_UNUSED) { 906 if (inst->src.addr_mode == MODE_UNUSED) {
935 dst = m68k_save_result(inst, dst, opts); 907 dst = m68k_save_result(inst, dst, opts);
936 } else {
937 dst = check_cycles(dst);
938 } 908 }
939 } 909 }
940 910
941 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) 911 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
942 { 912 {
990 dst = setcc_r(dst, CC_C, FLAG_C); 960 dst = setcc_r(dst, CC_C, FLAG_C);
991 dst = setcc_r(dst, CC_Z, FLAG_Z); 961 dst = setcc_r(dst, CC_Z, FLAG_Z);
992 dst = setcc_r(dst, CC_S, FLAG_N); 962 dst = setcc_r(dst, CC_S, FLAG_N);
993 dst = setcc_r(dst, CC_O, FLAG_V); 963 dst = setcc_r(dst, CC_O, FLAG_V);
994 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); 964 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
995 dst = check_cycles(dst);
996 dst = m68k_save_result(inst, dst, opts); 965 dst = m68k_save_result(inst, dst, opts);
997 break; 966 break;
998 case M68K_ADDX: 967 case M68K_ADDX:
999 break; 968 break;
1000 case M68K_AND: 969 case M68K_AND:
1016 } 985 }
1017 dst = mov_ir(dst, 0, FLAG_C, SZ_B); 986 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
1018 dst = setcc_r(dst, CC_Z, FLAG_Z); 987 dst = setcc_r(dst, CC_Z, FLAG_Z);
1019 dst = setcc_r(dst, CC_S, FLAG_N); 988 dst = setcc_r(dst, CC_S, FLAG_N);
1020 dst = mov_ir(dst, 0, FLAG_V, SZ_B); 989 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
1021 dst = check_cycles(dst);
1022 dst = m68k_save_result(inst, dst, opts); 990 dst = m68k_save_result(inst, dst, opts);
1023 break; 991 break;
1024 case M68K_ANDI_CCR: 992 case M68K_ANDI_CCR:
1025 case M68K_ANDI_SR: 993 case M68K_ANDI_SR:
1026 break; 994 break;
1098 } 1066 }
1099 dst = setcc_r(dst, CC_C, FLAG_C); 1067 dst = setcc_r(dst, CC_C, FLAG_C);
1100 dst = setcc_r(dst, CC_Z, FLAG_Z); 1068 dst = setcc_r(dst, CC_Z, FLAG_Z);
1101 dst = setcc_r(dst, CC_S, FLAG_N); 1069 dst = setcc_r(dst, CC_S, FLAG_N);
1102 dst = setcc_r(dst, CC_O, FLAG_V); 1070 dst = setcc_r(dst, CC_O, FLAG_V);
1103 dst = check_cycles(dst);
1104 break; 1071 break;
1105 case M68K_DIVS: 1072 case M68K_DIVS:
1106 case M68K_DIVU: 1073 case M68K_DIVU:
1107 break; 1074 break;
1108 case M68K_EOR: 1075 case M68K_EOR:
1124 } 1091 }
1125 dst = mov_ir(dst, 0, FLAG_C, SZ_B); 1092 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
1126 dst = setcc_r(dst, CC_Z, FLAG_Z); 1093 dst = setcc_r(dst, CC_Z, FLAG_Z);
1127 dst = setcc_r(dst, CC_S, FLAG_N); 1094 dst = setcc_r(dst, CC_S, FLAG_N);
1128 dst = mov_ir(dst, 0, FLAG_V, SZ_B); 1095 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
1129 dst = check_cycles(dst);
1130 dst = m68k_save_result(inst, dst, opts); 1096 dst = m68k_save_result(inst, dst, opts);
1131 break; 1097 break;
1132 case M68K_EORI_CCR: 1098 case M68K_EORI_CCR:
1133 case M68K_EORI_SR: 1099 case M68K_EORI_SR:
1134 case M68K_EXG: 1100 case M68K_EXG:
1151 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D); 1117 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
1152 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D); 1118 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
1153 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D); 1119 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
1154 } 1120 }
1155 } 1121 }
1156 dst = check_cycles(dst);
1157 break; 1122 break;
1158 case M68K_EXT: 1123 case M68K_EXT:
1159 break; 1124 break;
1160 case M68K_ILLEGAL: 1125 case M68K_ILLEGAL:
1161 dst = call(dst, (uint8_t *)m68k_save_context); 1126 dst = call(dst, (uint8_t *)m68k_save_context);
1177 case M68K_NEG: 1142 case M68K_NEG:
1178 case M68K_NEGX: 1143 case M68K_NEGX:
1179 break; 1144 break;
1180 case M68K_NOP: 1145 case M68K_NOP:
1181 dst = cycles(dst, BUS); 1146 dst = cycles(dst, BUS);
1182 dst = check_cycles(dst);
1183 break; 1147 break;
1184 case M68K_NOT: 1148 case M68K_NOT:
1185 break; 1149 break;
1186 case M68K_OR: 1150 case M68K_OR:
1187 dst = cycles(dst, BUS); 1151 dst = cycles(dst, BUS);
1202 } 1166 }
1203 dst = mov_ir(dst, 0, FLAG_C, SZ_B); 1167 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
1204 dst = setcc_r(dst, CC_Z, FLAG_Z); 1168 dst = setcc_r(dst, CC_Z, FLAG_Z);
1205 dst = setcc_r(dst, CC_S, FLAG_N); 1169 dst = setcc_r(dst, CC_S, FLAG_N);
1206 dst = mov_ir(dst, 0, FLAG_V, SZ_B); 1170 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
1207 dst = check_cycles(dst);
1208 dst = m68k_save_result(inst, dst, opts); 1171 dst = m68k_save_result(inst, dst, opts);
1209 break; 1172 break;
1210 case M68K_ORI_CCR: 1173 case M68K_ORI_CCR:
1211 case M68K_ORI_SR: 1174 case M68K_ORI_SR:
1212 case M68K_PEA: 1175 case M68K_PEA:
1241 dst = setcc_r(dst, CC_C, FLAG_C); 1204 dst = setcc_r(dst, CC_C, FLAG_C);
1242 dst = setcc_r(dst, CC_Z, FLAG_Z); 1205 dst = setcc_r(dst, CC_Z, FLAG_Z);
1243 dst = setcc_r(dst, CC_S, FLAG_N); 1206 dst = setcc_r(dst, CC_S, FLAG_N);
1244 dst = setcc_r(dst, CC_O, FLAG_V); 1207 dst = setcc_r(dst, CC_O, FLAG_V);
1245 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); 1208 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
1246 dst = check_cycles(dst);
1247 dst = m68k_save_result(inst, dst, opts); 1209 dst = m68k_save_result(inst, dst, opts);
1248 break; 1210 break;
1249 case M68K_SUBX: 1211 case M68K_SUBX:
1250 break; 1212 break;
1251 case M68K_SWAP: 1213 case M68K_SWAP:
1257 } 1219 }
1258 dst = mov_ir(dst, 0, FLAG_C, SZ_B); 1220 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
1259 dst = setcc_r(dst, CC_Z, FLAG_Z); 1221 dst = setcc_r(dst, CC_Z, FLAG_Z);
1260 dst = setcc_r(dst, CC_S, FLAG_N); 1222 dst = setcc_r(dst, CC_S, FLAG_N);
1261 dst = mov_ir(dst, 0, FLAG_V, SZ_B); 1223 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
1262 dst = check_cycles(dst);
1263 break; 1224 break;
1264 case M68K_TAS: 1225 case M68K_TAS:
1265 case M68K_TRAP: 1226 case M68K_TRAP:
1266 case M68K_TRAPV: 1227 case M68K_TRAPV:
1267 case M68K_TST: 1228 case M68K_TST:
1273 } 1234 }
1274 dst = setcc_r(dst, CC_C, FLAG_C); 1235 dst = setcc_r(dst, CC_C, FLAG_C);
1275 dst = setcc_r(dst, CC_Z, FLAG_Z); 1236 dst = setcc_r(dst, CC_Z, FLAG_Z);
1276 dst = setcc_r(dst, CC_S, FLAG_N); 1237 dst = setcc_r(dst, CC_S, FLAG_N);
1277 dst = setcc_r(dst, CC_O, FLAG_V); 1238 dst = setcc_r(dst, CC_O, FLAG_V);
1278 dst = check_cycles(dst);
1279 break; 1239 break;
1280 case M68K_UNLK: 1240 case M68K_UNLK:
1281 case M68K_INVALID: 1241 case M68K_INVALID:
1282 break; 1242 break;
1283 } 1243 }