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Fix lsl in new CPU core and make asl less broken
author Michael Pavone <pavone@retrodev.com>
date Sat, 15 Feb 2025 19:11:40 -0800
parents b0a7b1f708cc
children 9bd90cd94000
comparison
equal deleted inserted replaced
2609:fbb5115b1a27 2610:2de52352936c
1571 1571
1572 1110CCC1ZZ101RRR lsl_dn 1572 1110CCC1ZZ101RRR lsl_dn
1573 invalid Z 3 1573 invalid Z 3
1574 local shift 8 1574 local shift 8
1575 and dregs.C 63 shift 1575 and dregs.C 63 shift
1576 lsl dregs.R shift dregs.R Z 1576 switch Z
1577 update_flags XNZV0C 1577 case 2
1578 if shift >=U 32
1579 if shift = 32
1580 lsl dregs.R 31 dregs.R Z
1581 lsl dregs.R 1 dregs.R Z
1582 update_flags XN0Z1V0C
1583 else
1584 dregs.R:Z = 0
1585 update_flags X0N0Z1V0C0
1586 end
1587 else
1588 lsl dregs.R shift dregs.R Z
1589 update_flags NZV0C
1590 if shift
1591 xflag = cflag
1592 end
1593 end
1594 case 1
1595 if shift >=U 16
1596 if shift = 16
1597 lsl dregs.R 15 dregs.R Z
1598 lsl dregs.R 1 dregs.R Z
1599 update_flags XN0Z1V0C
1600 else
1601 dregs.R:Z = 0
1602 update_flags X0N0Z1V0C0
1603 end
1604 else
1605 lsl dregs.R shift dregs.R Z
1606 update_flags NZV0C
1607 if shift
1608 xflag = cflag
1609 end
1610 end
1611 case 0
1612 if shift >=U 8
1613 if shift = 8
1614 lsl dregs.R 7 dregs.R Z
1615 lsl dregs.R 1 dregs.R Z
1616 update_flags XN0Z1V0C
1617 else
1618 dregs.R:Z = 0
1619 update_flags X0N0Z1V0C0
1620 end
1621 else
1622 lsl dregs.R shift dregs.R Z
1623 update_flags NZV0C
1624 if shift
1625 xflag = cflag
1626 end
1627 end
1628 end
1578 add shift shift shift 1629 add shift shift shift
1579 switch Z 1630 switch Z
1580 case 2 1631 case 2
1581 add 4 shift shift 1632 add 4 shift shift
1582 default 1633 default
1626 1677
1627 1110CCC1ZZ100RRR asl_dn 1678 1110CCC1ZZ100RRR asl_dn
1628 invalid Z 3 1679 invalid Z 3
1629 local shift 8 1680 local shift 8
1630 and dregs.C 63 shift 1681 and dregs.C 63 shift
1631 lsl dregs.R shift dregs.R Z 1682 #TODO: implement loops and do this a bit at a time to implement V flag
1632 update_flags XNZV0C 1683 switch Z
1684 case 2
1685 if shift >=U 32
1686 if shift = 32
1687 lsl dregs.R 31 dregs.R Z
1688 lsl dregs.R 1 dregs.R Z
1689 update_flags XNZ1V0C
1690 else
1691 dregs.R:Z = 0
1692 update_flags X0N0Z1V0C0
1693 end
1694 else
1695 lsl dregs.R shift dregs.R Z
1696 update_flags NZV0C
1697 if shift
1698 xflag = cflag
1699 end
1700 end
1701 case 1
1702 if shift >=U 16
1703 if shift = 16
1704 lsl dregs.R 15 dregs.R Z
1705 lsl dregs.R 1 dregs.R Z
1706 update_flags XN0Z1V0C
1707 else
1708 dregs.R:Z = 0
1709 update_flags X0N0Z1V0C0
1710 end
1711 else
1712 lsl dregs.R shift dregs.R Z
1713 update_flags NZV0C
1714 if shift
1715 xflag = cflag
1716 end
1717 end
1718 case 0
1719 if shift >=U 8
1720 if shift = 8
1721 lsl dregs.R 7 dregs.R Z
1722 lsl dregs.R 1 dregs.R Z
1723 update_flags XN0Z1V0C
1724 else
1725 dregs.R:Z = 0
1726 update_flags X0N0Z1V0C0
1727 end
1728 else
1729 lsl dregs.R shift dregs.R Z
1730 update_flags NZV0C
1731 if shift
1732 xflag = cflag
1733 end
1734 end
1735 end
1633 add shift shift shift 1736 add shift shift shift
1634 switch Z 1737 switch Z
1635 case 2 1738 case 2
1636 add 4 shift shift 1739 add 4 shift shift
1637 default 1740 default