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Initial implementation of VDP register write breakpoints
author Michael Pavone <pavone@retrodev.com>
date Mon, 30 Oct 2023 00:07:56 -0700
parents 04d29635d238
children d3479965e631
comparison
equal deleted inserted replaced
2360:053ba4551c62 2361:3350b3c8faa8
1124 } 1124 }
1125 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1); 1125 context->fifo_read = (context->fifo_read+1) & (FIFO_SIZE-1);
1126 if (context->fifo_read == context->fifo_write) { 1126 if (context->fifo_read == context->fifo_write) {
1127 if ((context->cd & 0x20) && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_FILL) { 1127 if ((context->cd & 0x20) && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_FILL) {
1128 context->flags |= FLAG_DMA_RUN; 1128 context->flags |= FLAG_DMA_RUN;
1129 if (context->dma_hook) {
1130 context->dma_hook(context);
1131 }
1129 } 1132 }
1130 context->fifo_read = -1; 1133 context->fifo_read = -1;
1131 } 1134 }
1132 } else if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_COPY) { 1135 } else if ((context->flags & FLAG_DMA_RUN) && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_COPY) {
1133 if (context->flags & FLAG_READ_FETCHED) { 1136 if (context->flags & FLAG_READ_FETCHED) {
4703 //68K -> VDP DMA takes a few slots to actually start reading even though it acquires the bus immediately 4706 //68K -> VDP DMA takes a few slots to actually start reading even though it acquires the bus immediately
4704 //logic analyzer captures made it seem like the proper value is 4 slots, but that seems to cause trouble with the Nemesis' FIFO Wait State test 4707 //logic analyzer captures made it seem like the proper value is 4 slots, but that seems to cause trouble with the Nemesis' FIFO Wait State test
4705 //only captures are from a direct color DMA demo which will generally start DMA at a very specific point in display so other values are plausible 4708 //only captures are from a direct color DMA demo which will generally start DMA at a very specific point in display so other values are plausible
4706 //sticking with 3 slots for now until I can do some more captures 4709 //sticking with 3 slots for now until I can do some more captures
4707 vdp_run_context_full(context, context->cycles + 12 * ((context->regs[REG_MODE_2] & BIT_MODE_5) && (context->regs[REG_MODE_4] & BIT_H40) ? 4 : 5)); 4710 vdp_run_context_full(context, context->cycles + 12 * ((context->regs[REG_MODE_2] & BIT_MODE_5) && (context->regs[REG_MODE_4] & BIT_H40) ? 4 : 5));
4711 vdp_dma_started();
4708 context->flags |= FLAG_DMA_RUN; 4712 context->flags |= FLAG_DMA_RUN;
4709 vdp_dma_started(); 4713 if (context->dma_hook) {
4714 context->dma_hook(context);
4715 }
4710 return 1; 4716 return 1;
4711 } else { 4717 } else {
4712 context->flags |= FLAG_DMA_RUN; 4718 context->flags |= FLAG_DMA_RUN;
4719 if (context->dma_hook) {
4720 context->dma_hook(context);
4721 }
4713 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); 4722 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]);
4714 } 4723 }
4715 } else { 4724 } else {
4716 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd); 4725 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd);
4717 } 4726 }
4721 context->address = context->address_latch | (value & 0x3FFF); 4730 context->address = context->address_latch | (value & 0x3FFF);
4722 context->cd = (context->cd & 0x3C) | (value >> 14); 4731 context->cd = (context->cd & 0x3C) | (value >> 14);
4723 if ((value & 0xC000) == 0x8000) { 4732 if ((value & 0xC000) == 0x8000) {
4724 //Register write 4733 //Register write
4725 uint16_t reg = (value >> 8) & 0x1F; 4734 uint16_t reg = (value >> 8) & 0x1F;
4735 if (context->reg_hook) {
4736 context->reg_hook(context, reg, value);
4737 }
4726 vdp_reg_write(context, reg, value); 4738 vdp_reg_write(context, reg, value);
4727 } else if (mode_5) { 4739 } else if (mode_5) {
4728 context->flags |= FLAG_PENDING; 4740 context->flags |= FLAG_PENDING;
4729 //Should these be taken care of here or after the second write? 4741 //Should these be taken care of here or after the second write?
4730 //context->flags &= ~FLAG_READ_FETCHED; 4742 //context->flags &= ~FLAG_READ_FETCHED;
4771 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_FILL) { 4783 if (context->cd & 0x20 && (context->regs[REG_DMASRC_H] & DMA_TYPE_MASK) == DMA_FILL) {
4772 context->flags &= ~FLAG_DMA_RUN; 4784 context->flags &= ~FLAG_DMA_RUN;
4773 } 4785 }
4774 while (context->fifo_write == context->fifo_read) { 4786 while (context->fifo_write == context->fifo_read) {
4775 vdp_run_context_full(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)); 4787 vdp_run_context_full(context, context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20));
4788 }
4789 if (context->data_hook) {
4790 context->data_hook(context, value);
4776 } 4791 }
4777 fifo_entry * cur = context->fifo + context->fifo_write; 4792 fifo_entry * cur = context->fifo + context->fifo_write;
4778 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY; 4793 cur->cycle = context->cycles + ((context->regs[REG_MODE_4] & BIT_H40) ? 16 : 20)*FIFO_LATENCY;
4779 cur->address = context->address; 4794 cur->address = context->address;
4780 cur->value = value; 4795 cur->value = value;