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comparison m68k_core_x86.c @ 1942:35722beaf895

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Fix instruction timing for addq.w #i, (ay) in dynarec
author Michael Pavone <pavone@retrodev.com>
date Sat, 25 Apr 2020 18:10:40 -0700
parents 37afb9cf58be
children 0d87116630c7
comparison
equal deleted inserted replaced
1941:9eec86183aae 1942:35722beaf895
1313 } else if (size == OPSIZE_LONG) { 1313 } else if (size == OPSIZE_LONG) {
1314 if (inst->op == M68K_CMP) { 1314 if (inst->op == M68K_CMP) {
1315 numcycles = 6; 1315 numcycles = 6;
1316 } else if (inst->op == M68K_AND && inst->variant == VAR_IMMEDIATE) { 1316 } else if (inst->op == M68K_AND && inst->variant == VAR_IMMEDIATE) {
1317 numcycles = 6; 1317 numcycles = 6;
1318 } else if (inst->op == M68K_ADD && inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD && inst->variant == VAR_QUICK) {
1319 numcycles = 4;
1320 } else if (inst->dst.addr_mode <= MODE_AREG) { 1318 } else if (inst->dst.addr_mode <= MODE_AREG) {
1321 numcycles = inst->src.addr_mode <= MODE_AREG || inst->src.addr_mode == MODE_IMMEDIATE ? 8 : 6; 1319 numcycles = inst->src.addr_mode <= MODE_AREG || inst->src.addr_mode == MODE_IMMEDIATE ? 8 : 6;
1322 } else { 1320 } else {
1323 numcycles = 4; 1321 numcycles = 4;
1324 } 1322 }