comparison trans.c @ 1942:35722beaf895

Fix instruction timing for addq.w #i, (ay) in dynarec
author Michael Pavone <pavone@retrodev.com>
date Sat, 25 Apr 2020 18:10:40 -0700
parents 0c1491818f4b
children 374a5ae694e8 57ae42c3ab45
comparison
equal deleted inserted replaced
1941:9eec86183aae 1942:35722beaf895