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comparison z80_to_x86.c @ 1052:366c28ac6c55

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Implement undocumented flag bits for block LD instructions
author Michael Pavone <pavone@retrodev.com>
date Fri, 29 Jul 2016 09:14:32 -0700
parents 11ff5726fd5e
children b86c3ce007d9
comparison
equal deleted inserted replaced
1051:11ff5726fd5e 1052:366c28ac6c55
559 case Z80_LDI: { 559 case Z80_LDI: {
560 cycles(&opts->gen, num_cycles); 560 cycles(&opts->gen, num_cycles);
561 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); 561 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
562 call(code, opts->read_8); 562 call(code, opts->read_8);
563 zreg_to_native(opts, Z80_DE, opts->gen.scratch2); 563 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
564 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
564 call(code, opts->write_8); 565 call(code, opts->write_8);
566 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B);
567 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
568 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
569 and_ir(code, 0x8, opts->gen.scratch1, SZ_B);
570 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
571 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
572 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
565 cycles(&opts->gen, 2); 573 cycles(&opts->gen, 2);
566 if (opts->regs[Z80_DE] >= 0) { 574 if (opts->regs[Z80_DE] >= 0) {
567 add_ir(code, 1, opts->regs[Z80_DE], SZ_W); 575 add_ir(code, 1, opts->regs[Z80_DE], SZ_W);
568 } else { 576 } else {
569 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W); 577 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
586 case Z80_LDIR: { 594 case Z80_LDIR: {
587 cycles(&opts->gen, num_cycles); 595 cycles(&opts->gen, num_cycles);
588 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); 596 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
589 call(code, opts->read_8); 597 call(code, opts->read_8);
590 zreg_to_native(opts, Z80_DE, opts->gen.scratch2); 598 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
599 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
591 call(code, opts->write_8); 600 call(code, opts->write_8);
601 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B);
602 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
603 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
604 and_ir(code, 0x8, opts->gen.scratch1, SZ_B);
605 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
606 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
607 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
592 if (opts->regs[Z80_DE] >= 0) { 608 if (opts->regs[Z80_DE] >= 0) {
593 add_ir(code, 1, opts->regs[Z80_DE], SZ_W); 609 add_ir(code, 1, opts->regs[Z80_DE], SZ_W);
594 } else { 610 } else {
595 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W); 611 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
596 } 612 }
619 case Z80_LDD: { 635 case Z80_LDD: {
620 cycles(&opts->gen, num_cycles); 636 cycles(&opts->gen, num_cycles);
621 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); 637 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
622 call(code, opts->read_8); 638 call(code, opts->read_8);
623 zreg_to_native(opts, Z80_DE, opts->gen.scratch2); 639 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
640 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
624 call(code, opts->write_8); 641 call(code, opts->write_8);
642 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B);
643 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
644 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
645 and_ir(code, 0x8, opts->gen.scratch1, SZ_B);
646 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
647 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
648 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
625 cycles(&opts->gen, 2); 649 cycles(&opts->gen, 2);
626 if (opts->regs[Z80_DE] >= 0) { 650 if (opts->regs[Z80_DE] >= 0) {
627 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W); 651 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W);
628 } else { 652 } else {
629 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W); 653 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
646 case Z80_LDDR: { 670 case Z80_LDDR: {
647 cycles(&opts->gen, num_cycles); 671 cycles(&opts->gen, num_cycles);
648 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); 672 zreg_to_native(opts, Z80_HL, opts->gen.scratch1);
649 call(code, opts->read_8); 673 call(code, opts->read_8);
650 zreg_to_native(opts, Z80_DE, opts->gen.scratch2); 674 zreg_to_native(opts, Z80_DE, opts->gen.scratch2);
675 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
651 call(code, opts->write_8); 676 call(code, opts->write_8);
677 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B);
678 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
679 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
680 and_ir(code, 0x8, opts->gen.scratch1, SZ_B);
681 shl_ir(code, 4, opts->gen.scratch2, SZ_B);
682 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B);
683 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
652 if (opts->regs[Z80_DE] >= 0) { 684 if (opts->regs[Z80_DE] >= 0) {
653 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W); 685 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W);
654 } else { 686 } else {
655 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W); 687 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W);
656 } 688 }