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comparison m68k_to_x86.c @ 348:3923dbc2dcc4

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m68k_trap is now replaced with a generated one so it can call the generated memory acccess functions. The old static memory access functions have been removed from runtime.S
author Mike Pavone <pavone@retrodev.com>
date Tue, 21 May 2013 01:10:04 -0700
parents b24556b45d1e
children 91aa2aa05e68
comparison
equal deleted inserted replaced
347:b24556b45d1e 348:3923dbc2dcc4
29 void m68k_save_context(); 29 void m68k_save_context();
30 void m68k_load_context(); 30 void m68k_load_context();
31 void m68k_modified_ret_addr(); 31 void m68k_modified_ret_addr();
32 void m68k_native_addr(); 32 void m68k_native_addr();
33 void m68k_native_addr_and_sync(); 33 void m68k_native_addr_and_sync();
34 void m68k_trap();
35 void m68k_invalid(); 34 void m68k_invalid();
36 void m68k_retrans_stub(); 35 void m68k_retrans_stub();
37 void set_sr(); 36 void set_sr();
38 void set_ccr(); 37 void set_ccr();
39 void get_sr(); 38 void get_sr();
3088 uint8_t * passed = dst+1; 3087 uint8_t * passed = dst+1;
3089 dst = jcc(dst, CC_GE, dst+2); 3088 dst = jcc(dst, CC_GE, dst+2);
3090 dst = mov_ir(dst, 1, FLAG_N, SZ_B); 3089 dst = mov_ir(dst, 1, FLAG_N, SZ_B);
3091 dst = mov_ir(dst, VECTOR_CHK, SCRATCH2, SZ_D); 3090 dst = mov_ir(dst, VECTOR_CHK, SCRATCH2, SZ_D);
3092 dst = mov_ir(dst, inst->address+isize, SCRATCH1, SZ_D); 3091 dst = mov_ir(dst, inst->address+isize, SCRATCH1, SZ_D);
3093 dst = jmp(dst, (uint8_t *)m68k_trap); 3092 dst = jmp(dst, opts->trap);
3094 *passed = dst - (passed+1); 3093 *passed = dst - (passed+1);
3095 if (dst_op.mode == MODE_REG_DIRECT) { 3094 if (dst_op.mode == MODE_REG_DIRECT) {
3096 if (src_op.mode == MODE_REG_DIRECT) { 3095 if (src_op.mode == MODE_REG_DIRECT) {
3097 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size); 3096 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3098 } else if(src_op.mode == MODE_REG_DISPLACE8) { 3097 } else if(src_op.mode == MODE_REG_DISPLACE8) {
3110 passed = dst+1; 3109 passed = dst+1;
3111 dst = jcc(dst, CC_LE, dst+2); 3110 dst = jcc(dst, CC_LE, dst+2);
3112 dst = mov_ir(dst, 0, FLAG_N, SZ_B); 3111 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
3113 dst = mov_ir(dst, VECTOR_CHK, SCRATCH2, SZ_D); 3112 dst = mov_ir(dst, VECTOR_CHK, SCRATCH2, SZ_D);
3114 dst = mov_ir(dst, inst->address+isize, SCRATCH1, SZ_D); 3113 dst = mov_ir(dst, inst->address+isize, SCRATCH1, SZ_D);
3115 dst = jmp(dst, (uint8_t *)m68k_trap); 3114 dst = jmp(dst, opts->trap);
3116 *passed = dst - (passed+1); 3115 *passed = dst - (passed+1);
3117 dst = cycles(dst, 4); 3116 dst = cycles(dst, 4);
3118 break; 3117 break;
3119 } 3118 }
3120 case M68K_DIVS: 3119 case M68K_DIVS:
3150 dst = jcc(dst, CC_NZ, dst+2); 3149 dst = jcc(dst, CC_NZ, dst+2);
3151 dst = pop_r(dst, RAX); 3150 dst = pop_r(dst, RAX);
3152 dst = pop_r(dst, RDX); 3151 dst = pop_r(dst, RDX);
3153 dst = mov_ir(dst, VECTOR_INT_DIV_ZERO, SCRATCH2, SZ_D); 3152 dst = mov_ir(dst, VECTOR_INT_DIV_ZERO, SCRATCH2, SZ_D);
3154 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); 3153 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
3155 dst = jmp(dst, (uint8_t *)m68k_trap); 3154 dst = jmp(dst, opts->trap);
3156 *not_zero = dst - (not_zero+1); 3155 *not_zero = dst - (not_zero+1);
3157 if (inst->op == M68K_DIVS) { 3156 if (inst->op == M68K_DIVS) {
3158 dst = cdq(dst); 3157 dst = cdq(dst);
3159 } else { 3158 } else {
3160 dst = xor_rr(dst, RDX, RDX, SZ_D); 3159 dst = xor_rr(dst, RDX, RDX, SZ_D);
3851 break; 3850 break;
3852 //case M68K_TAS: 3851 //case M68K_TAS:
3853 case M68K_TRAP: 3852 case M68K_TRAP:
3854 dst = mov_ir(dst, src_op.disp + VECTOR_TRAP_0, SCRATCH2, SZ_D); 3853 dst = mov_ir(dst, src_op.disp + VECTOR_TRAP_0, SCRATCH2, SZ_D);
3855 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D); 3854 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
3856 dst = jmp(dst, (uint8_t *)m68k_trap); 3855 dst = jmp(dst, opts->trap);
3857 break; 3856 break;
3858 //case M68K_TRAPV: 3857 //case M68K_TRAPV:
3859 case M68K_TST: 3858 case M68K_TST:
3860 dst = cycles(dst, BUS); 3859 dst = cycles(dst, BUS);
3861 if (src_op.mode == MODE_REG_DIRECT) { 3860 if (src_op.mode == MODE_REG_DIRECT) {
4519 dst = cycles(dst, 24); 4518 dst = cycles(dst, 24);
4520 //discard function return address 4519 //discard function return address
4521 dst = pop_r(dst, SCRATCH2); 4520 dst = pop_r(dst, SCRATCH2);
4522 dst = jmp_r(dst, SCRATCH1); 4521 dst = jmp_r(dst, SCRATCH1);
4523 4522
4523 opts->trap = dst;
4524 dst = push_r(dst, SCRATCH2);
4525 //swap USP and SSP if not already in supervisor mode
4526 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B);
4527 already_supervisor = dst+1;
4528 dst = jcc(dst, CC_C, dst+2);
4529 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH2, SZ_D);
4530 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
4531 dst = mov_rr(dst, SCRATCH2, opts->aregs[7], SZ_D);
4532 *already_supervisor = dst - (already_supervisor+1);
4533 //save PC
4534 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
4535 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
4536 dst = call(dst, opts->write_32_lowfirst);
4537 //save status register
4538 dst = sub_ir(dst, 2, opts->aregs[7], SZ_D);
4539 dst = call(dst, (uint8_t *)get_sr);
4540 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
4541 dst = call(dst, opts->write_16);
4542 //set supervisor bit
4543 dst = or_irdisp8(dst, 0x20, CONTEXT, offsetof(m68k_context, status), SZ_B);
4544 //calculate vector address
4545 dst = pop_r(dst, SCRATCH1);
4546 dst = shl_ir(dst, 2, SCRATCH1, SZ_D);
4547 dst = call(dst, opts->read_32);
4548 dst = call(dst, (uint8_t *)m68k_native_addr_and_sync);
4549 dst = cycles(dst, 18);
4550 dst = jmp_r(dst, SCRATCH1);
4551
4524 opts->cur_code = dst; 4552 opts->cur_code = dst;
4525 } 4553 }
4526 4554
4527 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts) 4555 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts)
4528 { 4556 {