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comparison segacd.c @ 2137:3ef9456b76cf

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Fix a crash regression from word RAM interleave changes
author Michael Pavone <pavone@retrodev.com>
date Sat, 19 Mar 2022 00:42:05 -0700
parents 01fcbcba5cf8
children b6338e18787e
comparison
equal deleted inserted replaced
2136:01fcbcba5cf8 2137:3ef9456b76cf
279 m68k_context *m68k = vcontext; 279 m68k_context *m68k = vcontext;
280 genesis_context *gen = m68k->system; 280 genesis_context *gen = m68k->system;
281 segacd_context *cd = gen->expansion; 281 segacd_context *cd = gen->expansion;
282 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) { 282 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
283 cd->word_ram[address + cd->bank_toggle] = value; 283 cd->word_ram[address + cd->bank_toggle] = value;
284 m68k_invalidate_code_range(m68k, cd->base + address, address + 1); 284 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + address, cd->base + 0x200000 + address + 1);
285 } 285 }
286 return vcontext; 286 return vcontext;
287 } 287 }
288 288
289 static void *unmapped_word_write8(uint32_t address, void *vcontext, uint8_t value) 289 static void *unmapped_word_write8(uint32_t address, void *vcontext, uint8_t value)
298 cd->word_ram[offset] |= value; 298 cd->word_ram[offset] |= value;
299 } else { 299 } else {
300 cd->word_ram[address + cd->bank_toggle] &= 0xFF; 300 cd->word_ram[address + cd->bank_toggle] &= 0xFF;
301 cd->word_ram[address + cd->bank_toggle] |= value << 8; 301 cd->word_ram[address + cd->bank_toggle] |= value << 8;
302 } 302 }
303 m68k_invalidate_code_range(m68k, cd->base + (address & ~1), address + 1); 303 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + (address & ~1), cd->base + 0x200000 + address + 1);
304 } 304 }
305 return vcontext; 305 return vcontext;
306 } 306 }
307 307
308 static uint32_t cell_image_translate_address(uint32_t address) 308 static uint32_t cell_image_translate_address(uint32_t address)