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comparison cpu_dsl.py @ 1697:44d8c6e61ad4

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Added new sext instruction for sign extension to CPU sdl
author Michael Pavone <pavone@retrodev.com>
date Fri, 25 Jan 2019 13:45:58 -0800
parents ca158bc091f9
children 90272218469c
comparison
equal deleted inserted replaced
1695:3c34122754ac 1697:44d8c6e61ad4
370 370
371 def _asrCImpl(prog, params, rawParams): 371 def _asrCImpl(prog, params, rawParams):
372 shiftSize = prog.paramSize(rawParams[0]) 372 shiftSize = prog.paramSize(rawParams[0])
373 mask = 1 << (shiftSize - 1) 373 mask = 1 << (shiftSize - 1)
374 return '\n\t{dst} = ({a} >> {b}) | ({a} & {mask});'.format(a = params[0], b = params[1], dst = params[2], mask = mask) 374 return '\n\t{dst} = ({a} >> {b}) | ({a} & {mask});'.format(a = params[0], b = params[1], dst = params[2], mask = mask)
375
376 def _sext(size, src):
377 if size == 16:
378 return src | 0xFF00 if src & 0x80 else src
379 else:
380 return src | 0xFFFF0000 if src & 0x8000 else src
381
382 def _sextCImpl(prog, params, rawParms):
383 if params[0] == 16:
384 fmt = '\n\t{dst} = {src} & 0x80 ? {src} | 0xFF00 : {src};'
385 else:
386 fmt = '\n\t{dst} = {src} & 0x8000 ? {src} | 0xFFFF0000 : {src};'
387 return fmt.format(src=params[1], dst=params[2])
375 388
376 _opMap = { 389 _opMap = {
377 'mov': Op(lambda val: val).cUnaryOperator(''), 390 'mov': Op(lambda val: val).cUnaryOperator(''),
378 'not': Op(lambda val: ~val).cUnaryOperator('~'), 391 'not': Op(lambda val: ~val).cUnaryOperator('~'),
379 'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'), 392 'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'),
388 'xor': Op(lambda a, b: a ^ b).cBinaryOperator('^'), 401 'xor': Op(lambda a, b: a ^ b).cBinaryOperator('^'),
389 'abs': Op(lambda val: abs(val)).addImplementation( 402 'abs': Op(lambda val: abs(val)).addImplementation(
390 'c', 1, lambda prog, params: '\n\t{dst} = abs({src});'.format(dst=params[1], src=params[0]) 403 'c', 1, lambda prog, params: '\n\t{dst} = abs({src});'.format(dst=params[1], src=params[0])
391 ), 404 ),
392 'cmp': Op().addImplementation('c', None, _cmpCImpl), 405 'cmp': Op().addImplementation('c', None, _cmpCImpl),
406 'sext': Op(_sext).addImplementation('c', 2, _sextCImpl),
393 'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format( 407 'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format(
394 pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]]) 408 pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]])
395 )), 409 )),
396 'cycles': Op().addImplementation('c', None, 410 'cycles': Op().addImplementation('c', None,
397 lambda prog, params: '\n\tcontext->cycles += context->opts->gen.clock_divider * {0};'.format( 411 lambda prog, params: '\n\tcontext->cycles += context->opts->gen.clock_divider * {0};'.format(