Mercurial > repos > blastem
comparison m68k_to_x86.c @ 100:45cd7d3e7918
Implement areg indexed mode for lea
author | Mike Pavone <pavone@retrodev.com> |
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date | Thu, 27 Dec 2012 22:11:26 -0800 |
parents | 8491de5d6c06 |
children | bfaca67eeb78 |
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99:8491de5d6c06 | 100:45cd7d3e7918 |
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1137 return dst; | 1137 return dst; |
1138 } | 1138 } |
1139 | 1139 |
1140 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) | 1140 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts) |
1141 { | 1141 { |
1142 int8_t dst_reg = native_reg(&(inst->dst), opts); | 1142 int8_t dst_reg = native_reg(&(inst->dst), opts), sec_reg; |
1143 switch(inst->src.addr_mode) | 1143 switch(inst->src.addr_mode) |
1144 { | 1144 { |
1145 case MODE_AREG_INDIRECT: | 1145 case MODE_AREG_INDIRECT: |
1146 dst = cycles(dst, BUS); | 1146 dst = cycles(dst, BUS); |
1147 if (opts->aregs[inst->src.params.regs.pri] >= 0) { | 1147 if (opts->aregs[inst->src.params.regs.pri] >= 0) { |
1174 } else { | 1174 } else { |
1175 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); | 1175 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D); |
1176 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D); | 1176 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D); |
1177 } | 1177 } |
1178 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->src)), SZ_D); | 1178 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->src)), SZ_D); |
1179 } | |
1180 break; | |
1181 case MODE_AREG_INDEX_DISP8: | |
1182 dst = cycles(dst, 6);//TODO: Check to make sure this is correct | |
1183 if (opts->aregs[inst->src.params.regs.pri] >= 0) { | |
1184 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH2, SZ_D); | |
1185 } else { | |
1186 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH2, SZ_D); | |
1187 } | |
1188 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7; | |
1189 if (inst->src.params.regs.sec & 1) { | |
1190 if (inst->src.params.regs.sec & 0x10) { | |
1191 if (opts->aregs[sec_reg] >= 0) { | |
1192 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D); | |
1193 } else { | |
1194 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); | |
1195 } | |
1196 } else { | |
1197 if (opts->dregs[sec_reg] >= 0) { | |
1198 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D); | |
1199 } else { | |
1200 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D); | |
1201 } | |
1202 } | |
1203 } else { | |
1204 if (inst->src.params.regs.sec & 0x10) { | |
1205 if (opts->aregs[sec_reg] >= 0) { | |
1206 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D); | |
1207 } else { | |
1208 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); | |
1209 } | |
1210 } else { | |
1211 if (opts->dregs[sec_reg] >= 0) { | |
1212 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D); | |
1213 } else { | |
1214 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D); | |
1215 } | |
1216 } | |
1217 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D); | |
1218 } | |
1219 if (inst->src.params.regs.displacement) { | |
1220 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH2, SZ_D); | |
1221 } | |
1222 if (dst_reg >= 0) { | |
1223 dst = mov_rr(dst, SCRATCH2, dst_reg, SZ_D); | |
1224 } else { | |
1225 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->src)), SZ_D); | |
1179 } | 1226 } |
1180 break; | 1227 break; |
1181 case MODE_PC_DISPLACE: | 1228 case MODE_PC_DISPLACE: |
1182 dst = cycles(dst, 8); | 1229 dst = cycles(dst, 8); |
1183 if (dst_reg >= 0) { | 1230 if (dst_reg >= 0) { |