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comparison gen_arm.c @ 554:474270dbff15

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Fix ARM code generation and test program
author Michael Pavone <pavone@retrodev.com>
date Sun, 23 Feb 2014 22:17:43 -0800
parents 1af6c1052993
children c8fefa140c80
comparison
equal deleted inserted replaced
553:1af6c1052993 554:474270dbff15
49 #define OFF_REG 0x2000000u 49 #define OFF_REG 0x2000000u
50 50
51 #define PUSH (OP_STR | PRE_IND | OFF_IMM | SZ_W | WRITE_B | DIR_DOWN | sizeof(uint32_t) | (sp << 16)) 51 #define PUSH (OP_STR | PRE_IND | OFF_IMM | SZ_W | WRITE_B | DIR_DOWN | sizeof(uint32_t) | (sp << 16))
52 #define POP (OP_LDR | POST_IND | OFF_IMM | SZ_W | DIR_UP | sizeof(uint32_t) | (sp << 16)) 52 #define POP (OP_LDR | POST_IND | OFF_IMM | SZ_W | DIR_UP | sizeof(uint32_t) | (sp << 16))
53 #define PUSHM (OP_STM | PRE_IND | SZ_W | WRITE_B | DIR_DOWN | (sp << 16)) 53 #define PUSHM (OP_STM | PRE_IND | SZ_W | WRITE_B | DIR_DOWN | (sp << 16))
54 #define POPM (OP_LDM | POST_IND | SZ_W | DIR_UP | (sp << 16)) 54 #define POPM (OP_LDM | POST_IND | SZ_W | WRITE_B | DIR_UP | (sp << 16))
55 55
56 #define IMMED 0x2000000u 56 #define IMMED 0x2000000u
57 #define REG 0u 57 #define REG 0u
58 58
59 59
85 code->last = code->cur + size/sizeof(uint32_t) - RESERVE_INSTRUCTIONS; 85 code->last = code->cur + size/sizeof(uint32_t) - RESERVE_INSTRUCTIONS;
86 } 86 }
87 87
88 void check_alloc_code(code_info *code) 88 void check_alloc_code(code_info *code)
89 { 89 {
90 if (code->cur = code->last) { 90 if (code->cur == code->last) {
91 size_t size = CODE_ALLOC_SIZE; 91 size_t size = CODE_ALLOC_SIZE;
92 uint32_t *next_code = alloc_code(&size); 92 uint32_t *next_code = alloc_code(&size);
93 if (!next_code) { 93 if (!next_code) {
94 fputs("Failed to allocate memory for generated code\n", stderr); 94 fputs("Failed to allocate memory for generated code\n", stderr);
95 exit(1); 95 exit(1);
125 } 125 }
126 126
127 uint32_t data_proc(code_info *code, uint32_t cond, uint32_t op, uint32_t set_cond, uint32_t dst, uint32_t src1, uint32_t src2) 127 uint32_t data_proc(code_info *code, uint32_t cond, uint32_t op, uint32_t set_cond, uint32_t dst, uint32_t src1, uint32_t src2)
128 { 128 {
129 check_alloc_code(code); 129 check_alloc_code(code);
130 *(code->cur++) = cond | op | set_cond | (dst << 16) | (src1 << 12) | src2; 130 *(code->cur++) = cond | op | set_cond | (src1 << 16) | (dst << 12) | src2;
131 131
132 return CODE_OK; 132 return CODE_OK;
133 } 133 }
134 134
135 uint32_t data_proci(code_info *code, uint32_t cond, uint32_t op, uint32_t set_cond, uint32_t dst, uint32_t src1, uint32_t immed) 135 uint32_t data_proci(code_info *code, uint32_t cond, uint32_t op, uint32_t set_cond, uint32_t dst, uint32_t src1, uint32_t immed)
136 { 136 {
137 immed = make_immed(immed); 137 immed = make_immed(immed);
138 if (immed = INVALID_IMMED) { 138 if (immed == INVALID_IMMED) {
139 return immed; 139 return immed;
140 } 140 }
141 return data_proc(code, cond, op, set_cond, dst, src1, immed); 141 return data_proc(code, cond, op | IMMED, set_cond, dst, src1, immed);
142 } 142 }
143 143
144 //TODO: support shifted register for op2 144 //TODO: support shifted register for op2
145 145
146 uint32_t and(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond) 146 uint32_t and(code_info *code, uint32_t dst, uint32_t src1, uint32_t src2, uint32_t set_cond)