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Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
author Mike Pavone <pavone@retrodev.com>
date Thu, 13 Dec 2012 09:47:40 -0800
parents f2aaaf36c875
children 937b47c9b79b
comparison
equal deleted inserted replaced
49:d2e43d64e999 50:4836d1f3841a
1006 break; 1006 break;
1007 } 1007 }
1008 decoded->extra.size = (*istream >> 6) & 0x3; 1008 decoded->extra.size = (*istream >> 6) & 0x3;
1009 immed = (*istream >> 9) & 0x7; 1009 immed = (*istream >> 9) & 0x7;
1010 if (*istream & 0x100) { 1010 if (*istream & 0x100) {
1011 decoded->src.addr_mode = MODE_IMMEDIATE;
1012 decoded->src.params.immed = immed;
1013 } else {
1014 decoded->src.addr_mode = MODE_REG; 1011 decoded->src.addr_mode = MODE_REG;
1015 decoded->src.params.regs.pri = immed; 1012 decoded->src.params.regs.pri = immed;
1013 } else {
1014 decoded->src.addr_mode = MODE_IMMEDIATE;
1015 if (!immed) {
1016 immed = 8;
1017 }
1018 decoded->src.params.immed = immed;
1016 } 1019 }
1017 decoded->dst.addr_mode = MODE_REG; 1020 decoded->dst.addr_mode = MODE_REG;
1018 decoded->dst.params.regs.pri = *istream & 0x7; 1021 decoded->dst.params.regs.pri = *istream & 0x7;
1019 1022
1020 } else { 1023 } else {
1065 "lsr", 1068 "lsr",
1066 "move", 1069 "move",
1067 "move",//ccr 1070 "move",//ccr
1068 "move",//from_sr 1071 "move",//from_sr
1069 "move",//sr 1072 "move",//sr
1070 "move_usp", 1073 "move",//usp
1071 "movem", 1074 "movem",
1072 "movep", 1075 "movep",
1073 "muls", 1076 "muls",
1074 "mulu", 1077 "mulu",
1075 "nbcd", 1078 "nbcd",
1215 case M68K_DBCC: 1218 case M68K_DBCC:
1216 case M68K_SCC: 1219 case M68K_SCC:
1217 ret = strlen(mnemonics[decoded->op]) - 2; 1220 ret = strlen(mnemonics[decoded->op]) - 2;
1218 memcpy(dst, mnemonics[decoded->op], ret); 1221 memcpy(dst, mnemonics[decoded->op], ret);
1219 dst[ret] = 0; 1222 dst[ret] = 0;
1220 strcat(dst, cond_mnem[decoded->extra.cond]); 1223 strcpy(dst+ret, cond_mnem[decoded->extra.cond]);
1221 ret = strlen(dst); 1224 ret = strlen(dst);
1225 if (decoded->op != M68K_SCC) {
1226 ret += sprintf(dst+ret, " #%d <%X>", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed);
1227 return ret;
1228 }
1222 break; 1229 break;
1223 case M68K_BSR: 1230 case M68K_BSR:
1224 ret = sprintf(dst, "bsr%s", decoded->variant == VAR_BYTE ? ".s" : ""); 1231 ret = sprintf(dst, "bsr%s #%d <%X>", decoded->variant == VAR_BYTE ? ".s" : "", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed);
1225 break; 1232 return ret;
1226 case M68K_MOVE_FROM_SR: 1233 case M68K_MOVE_FROM_SR:
1227 ret = sprintf(dst, "%s", mnemonics[decoded->op]); 1234 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
1228 ret += sprintf(dst + ret, " SR"); 1235 ret += sprintf(dst + ret, " SR");
1229 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 1); 1236 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 1);
1230 return ret; 1237 return ret;
1238 case M68K_MOVE_CCR: 1245 case M68K_MOVE_CCR:
1239 case M68K_ORI_CCR: 1246 case M68K_ORI_CCR:
1240 ret = sprintf(dst, "%s", mnemonics[decoded->op]); 1247 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
1241 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0); 1248 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0);
1242 ret += sprintf(dst + ret, ", %s", special_op); 1249 ret += sprintf(dst + ret, ", %s", special_op);
1250 return ret;
1251 case M68K_MOVE_USP:
1252 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
1253 if (decoded->src.addr_mode != MODE_UNUSED) {
1254 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0);
1255 ret += sprintf(dst + ret, ", USP");
1256 } else {
1257 ret += sprintf(dst + ret, "USP, ");
1258 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0);
1259 }
1243 return ret; 1260 return ret;
1244 default: 1261 default:
1245 size = decoded->extra.size; 1262 size = decoded->extra.size;
1246 ret = sprintf(dst, "%s%s%s", 1263 ret = sprintf(dst, "%s%s%s",
1247 mnemonics[decoded->op], 1264 mnemonics[decoded->op],