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comparison blastem.c @ 482:4b24260125f3

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Theoretically more correct timing of Z80 bus request
author Mike Pavone <pavone@retrodev.com>
date Wed, 18 Sep 2013 19:10:54 -0700
parents f065769836e8
children 3e1573fa22cf
comparison
equal deleted inserted replaced
481:1f3450d1129f 482:4b24260125f3
515 gen->ports[2].control = value; 515 gen->ports[2].control = value;
516 break; 516 break;
517 } 517 }
518 } else { 518 } else {
519 if (location == 0x1100) { 519 if (location == 0x1100) {
520 sync_z80(gen->z80, context->current_cycle * MCLKS_PER_68K);
521 if (busack_cycle <= context->current_cycle) { 520 if (busack_cycle <= context->current_cycle) {
522 busack = new_busack; 521 busack = new_busack;
523 busack_cycle = CYCLE_NEVER; 522 busack_cycle = CYCLE_NEVER;
524 } 523 }
525 if (value & 1) { 524 if (value & 1) {
526 dputs("bus requesting Z80"); 525 dputs("bus requesting Z80");
527 526
528 if(!reset && !busreq) { 527 if(!reset && !busreq) {
529 busack_cycle = ((gen->z80->current_cycle + Z80_ACK_DELAY) * MCLKS_PER_Z80) / MCLKS_PER_68K;//context->current_cycle + Z80_ACK_DELAY; 528 sync_z80(gen->z80, context->current_cycle * MCLKS_PER_68K + Z80_ACK_DELAY*MCLKS_PER_Z80);
529 busack_cycle = (gen->z80->current_cycle * MCLKS_PER_Z80) / MCLKS_PER_68K;//context->current_cycle + Z80_ACK_DELAY;
530 new_busack = Z80_REQ_ACK; 530 new_busack = Z80_REQ_ACK;
531 } 531 }
532 busreq = 1; 532 busreq = 1;
533 } else { 533 } else {
534 sync_z80(gen->z80, context->current_cycle * MCLKS_PER_68K);
534 if (busreq) { 535 if (busreq) {
535 dputs("releasing z80 bus"); 536 dputs("releasing z80 bus");
536 #ifdef DO_DEBUG_PRINT 537 #ifdef DO_DEBUG_PRINT
537 char fname[20]; 538 char fname[20];
538 sprintf(fname, "zram-%d", zram_counter++); 539 sprintf(fname, "zram-%d", zram_counter++);