comparison cpu_dsl.py @ 1701:4fd34fde390c

Added adc instruction to CPU DSL
author Michael Pavone <pavone@retrodev.com>
date Sun, 27 Jan 2019 05:55:08 -0800
parents e4b4e21a37fa
children 73ac2e59fa3f
comparison
equal deleted inserted replaced
1700:e4b4e21a37fa 1701:4fd34fde390c
383 if params[0] == 16: 383 if params[0] == 16:
384 fmt = '\n\t{dst} = {src} & 0x80 ? {src} | 0xFF00 : {src};' 384 fmt = '\n\t{dst} = {src} & 0x80 ? {src} | 0xFF00 : {src};'
385 else: 385 else:
386 fmt = '\n\t{dst} = {src} & 0x8000 ? {src} | 0xFFFF0000 : {src};' 386 fmt = '\n\t{dst} = {src} & 0x8000 ? {src} | 0xFFFF0000 : {src};'
387 return fmt.format(src=params[1], dst=params[2]) 387 return fmt.format(src=params[1], dst=params[2])
388 388
389 def _adcCImpl(prog, params, rawParams):
390 carryFlag = None
391 for flag in prog.flags.flagCalc:
392 if prog.flags.flagCalc[flag] == 'carry':
393 carryFlag = flag
394 if carryFlag is None:
395 raise Exception('adc requires a defined carry flag')
396 base = '\n\t{dst} = {a} + {b} + ('.format(dst = params[2], a = params[0], b = params[1])
397 carryStorage = prog.flags.getStorage(carryFlag)
398 if type(carryStorage) is tuple:
399 reg,bit = carryStorage
400 reg = prog.resolveReg(reg, None, (), False)
401 check = '({reg} & 1 << {bit})'.format(reg=reg, bit=bit)
402 else:
403 check = prog.resolveReg(carryStorage, None, (), False)
404 return base + check + ' ? 1 : 0);'
405
389 _opMap = { 406 _opMap = {
390 'mov': Op(lambda val: val).cUnaryOperator(''), 407 'mov': Op(lambda val: val).cUnaryOperator(''),
391 'not': Op(lambda val: ~val).cUnaryOperator('~'), 408 'not': Op(lambda val: ~val).cUnaryOperator('~'),
392 'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'), 409 'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'),
393 'neg': Op(lambda val: -val).cUnaryOperator('-'), 410 'neg': Op(lambda val: -val).cUnaryOperator('-'),
394 'add': Op(lambda a, b: a + b).cBinaryOperator('+'), 411 'add': Op(lambda a, b: a + b).cBinaryOperator('+'),
412 'adc': Op().addImplementation('c', 2, _adcCImpl),
395 'sub': Op(lambda a, b: b - a).cBinaryOperator('-'), 413 'sub': Op(lambda a, b: b - a).cBinaryOperator('-'),
396 'lsl': Op(lambda a, b: a << b).cBinaryOperator('<<'), 414 'lsl': Op(lambda a, b: a << b).cBinaryOperator('<<'),
397 'lsr': Op(lambda a, b: a >> b).cBinaryOperator('>>'), 415 'lsr': Op(lambda a, b: a >> b).cBinaryOperator('>>'),
398 'asr': Op(lambda a, b: a >> b).addImplementation('c', 2, _asrCImpl), 416 'asr': Op(lambda a, b: a >> b).addImplementation('c', 2, _asrCImpl),
399 'and': Op(lambda a, b: a & b).cBinaryOperator('&'), 417 'and': Op(lambda a, b: a & b).cBinaryOperator('&'),