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comparison vdp.c @ 1174:500d8deea802

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Fix H32 VInt timing inconsistency
author Michael Pavone <pavone@retrodev.com>
date Mon, 16 Jan 2017 23:34:30 -0800
parents d0f67c59b756
children 0e0386fa795c
comparison
equal deleted inserted replaced
1173:d0f67c59b756 1174:500d8deea802
23 #define SCROLL_BUFFER_MASK (SCROLL_BUFFER_SIZE-1) 23 #define SCROLL_BUFFER_MASK (SCROLL_BUFFER_SIZE-1)
24 #define SCROLL_BUFFER_DRAW (SCROLL_BUFFER_SIZE/2) 24 #define SCROLL_BUFFER_DRAW (SCROLL_BUFFER_SIZE/2)
25 25
26 #define MCLKS_SLOT_H40 16 26 #define MCLKS_SLOT_H40 16
27 #define MCLKS_SLOT_H32 20 27 #define MCLKS_SLOT_H32 20
28 #define VINT_SLOT_H40 255 //21 slots before HSYNC, 16 during, 10 after 28 #define VINT_SLOT_H40 0 //21 slots before HSYNC, 16 during, 10 after
29 #define VINT_SLOT_H32 255 //old value was 23, but recent tests suggest the actual value is close to the H40 one 29 #define VINT_SLOT_H32 0 //old value was 23, but recent tests suggest the actual value is close to the H40 one
30 #define VINT_SLOT_MODE4 4 30 #define VINT_SLOT_MODE4 4
31 #define HSYNC_SLOT_H40 230 31 #define HSYNC_SLOT_H40 230
32 #define HSYNC_END_H40 (HSYNC_SLOT_H40+17) 32 #define HSYNC_END_H40 (HSYNC_SLOT_H40+17)
33 #define HBLANK_START_H40 178 //should be 179 according to Nemesis, but 178 seems to fit slightly better with my test ROM results 33 #define HBLANK_START_H40 178 //should be 179 according to Nemesis, but 178 seems to fit slightly better with my test ROM results
34 #define HBLANK_END_H40 0 //should be 5.5 according to Nemesis, but 0 seems to fit better with my test ROM results 34 #define HBLANK_END_H40 0 //should be 5.5 according to Nemesis, but 0 seems to fit better with my test ROM results
2123 index_reset_slot = 165; 2123 index_reset_slot = 165;
2124 bg_end_slot = BG_START_SLOT + 320/2; 2124 bg_end_slot = BG_START_SLOT + 320/2;
2125 max_draws = MAX_DRAWS-1; 2125 max_draws = MAX_DRAWS-1;
2126 max_sprites = MAX_SPRITES_LINE; 2126 max_sprites = MAX_SPRITES_LINE;
2127 index_reset_value = 0x80; 2127 index_reset_value = 0x80;
2128 vint_slot = (VINT_SLOT_H40+1) & 0xFF; 2128 vint_slot = VINT_SLOT_H40;
2129 line_change = LINE_CHANGE_H40; 2129 line_change = LINE_CHANGE_H40;
2130 jump_start = 182; 2130 jump_start = 182;
2131 jump_dest = 229; 2131 jump_dest = 229;
2132 } else { 2132 } else {
2133 bg_end_slot = BG_START_SLOT + 256/2; 2133 bg_end_slot = BG_START_SLOT + 256/2;
2134 max_draws = MAX_DRAWS_H32-1; 2134 max_draws = MAX_DRAWS_H32-1;
2135 max_sprites = MAX_SPRITES_LINE_H32; 2135 max_sprites = MAX_SPRITES_LINE_H32;
2136 buf_clear_slot = 128; 2136 buf_clear_slot = 128;
2137 index_reset_slot = 132; 2137 index_reset_slot = 132;
2138 index_reset_value = 0x80; 2138 index_reset_value = 0x80;
2139 vint_slot = (VINT_SLOT_H32+1) & 0xFF; 2139 vint_slot = VINT_SLOT_H32;
2140 line_change = LINE_CHANGE_H32; 2140 line_change = LINE_CHANGE_H32;
2141 jump_start = 147; 2141 jump_start = 147;
2142 jump_dest = 233; 2142 jump_dest = 233;
2143 } 2143 }
2144 vint_line = context->inactive_start; 2144 vint_line = context->inactive_start;
2777 } 2777 }
2778 cycles += (VINT_SLOT_H40 - (context->hslot > HSYNC_END_H40 ? context->hslot : HSYNC_END_H40)) * MCLKS_SLOT_H40; 2778 cycles += (VINT_SLOT_H40 - (context->hslot > HSYNC_END_H40 ? context->hslot : HSYNC_END_H40)) * MCLKS_SLOT_H40;
2779 return cycles; 2779 return cycles;
2780 } 2780 }
2781 } else { 2781 } else {
2782 if (context->hslot >= LINE_CHANGE_H32 && context->hslot <= VINT_SLOT_H32) { 2782 if (context->hslot >= LINE_CHANGE_H32 || context->hslot <= VINT_SLOT_H32) {
2783 if (context->hslot < 233) { 2783 if (context->hslot <= VINT_SLOT_H32) {
2784 return context->cycles + (148 - context->hslot + VINT_SLOT_H40 - 233) * MCLKS_SLOT_H32; 2784 return context->cycles + (VINT_SLOT_H32 - context->hslot) * MCLKS_SLOT_H32;
2785 } else if (context->hslot < 233) {
2786 return context->cycles + (VINT_SLOT_H32 + 256 - 233 + 148 - context->hslot) * MCLKS_SLOT_H32;
2785 } else { 2787 } else {
2786 return context->cycles + (VINT_SLOT_H32 - context->hslot) * MCLKS_SLOT_H32; 2788 return context->cycles + (VINT_SLOT_H32 + 256 - context->hslot) * MCLKS_SLOT_H32;
2787 } 2789 }
2788 } 2790 }
2789 } 2791 }
2790 } else { 2792 } else {
2791 if (context->hslot >= LINE_CHANGE_H40) { 2793 if (context->hslot >= LINE_CHANGE_H40) {
2799 int32_t cycles_to_vint = vdp_cycles_to_line(context, vint_line); 2801 int32_t cycles_to_vint = vdp_cycles_to_line(context, vint_line);
2800 if (context->regs[REG_MODE_2] & BIT_MODE_5) { 2802 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
2801 if (context->regs[REG_MODE_4] & BIT_H40) { 2803 if (context->regs[REG_MODE_4] & BIT_H40) {
2802 cycles_to_vint += MCLKS_LINE - (LINE_CHANGE_H40 + (256 - VINT_SLOT_H40)) * MCLKS_SLOT_H40; 2804 cycles_to_vint += MCLKS_LINE - (LINE_CHANGE_H40 + (256 - VINT_SLOT_H40)) * MCLKS_SLOT_H40;
2803 } else { 2805 } else {
2804 cycles_to_vint += (VINT_SLOT_H32 - 233 + 148 - LINE_CHANGE_H32) * MCLKS_SLOT_H32; 2806 cycles_to_vint += (VINT_SLOT_H32 + 256 - 233 + 148 - LINE_CHANGE_H32) * MCLKS_SLOT_H32;
2805 } 2807 }
2806 } else { 2808 } else {
2807 cycles_to_vint += (256 - LINE_CHANGE_MODE4 + VINT_SLOT_MODE4) * MCLKS_SLOT_H32; 2809 cycles_to_vint += (256 - LINE_CHANGE_MODE4 + VINT_SLOT_MODE4) * MCLKS_SLOT_H32;
2808 } 2810 }
2809 return context->cycles + cycles_to_vint; 2811 return context->cycles + cycles_to_vint;