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comparison blastem.c @ 736:535e97bad27f

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Implement cycles being stolen from 68K when the Z80 accesses the bank area or VDP/PSG. Small fix to code that tries to get system into a consistent state for a savestate
author Michael Pavone <pavone@retrodev.com>
date Mon, 25 May 2015 23:37:13 -0700
parents 20be7d01e312
children 296ddfcf0d43
comparison
equal deleted inserted replaced
735:539d12fa6a4d 736:535e97bad27f
215 vdp_context * v_context = gen->vdp; 215 vdp_context * v_context = gen->vdp;
216 z80_context * z_context = gen->z80; 216 z80_context * z_context = gen->z80;
217 uint32_t mclks = context->current_cycle; 217 uint32_t mclks = context->current_cycle;
218 sync_z80(z_context, mclks); 218 sync_z80(z_context, mclks);
219 sync_sound(gen, mclks); 219 sync_sound(gen, mclks);
220 while (context->current_cycle > mclks) {
221 mclks = context->current_cycle;
222 sync_z80(z_context, mclks);
223 sync_sound(gen, mclks);
224 }
220 vdp_run_context(v_context, mclks); 225 vdp_run_context(v_context, mclks);
221 if (v_context->frame != last_frame_num) { 226 if (v_context->frame != last_frame_num) {
222 //printf("reached frame end %d | MCLK Cycles: %d, Target: %d, VDP cycles: %d, vcounter: %d, hslot: %d\n", last_frame_num, mclks, gen->frame_end, v_context->cycles, v_context->vcounter, v_context->hslot); 227 //printf("reached frame end %d | MCLK Cycles: %d, Target: %d, VDP cycles: %d, vcounter: %d, hslot: %d\n", last_frame_num, mclks, gen->frame_end, v_context->cycles, v_context->vcounter, v_context->hslot);
223 last_frame_num = v_context->frame; 228 last_frame_num = v_context->frame;
224 229
258 if (address) { 263 if (address) {
259 if (break_on_sync) { 264 if (break_on_sync) {
260 break_on_sync = 0; 265 break_on_sync = 0;
261 debugger(context, address); 266 debugger(context, address);
262 } 267 }
263 if (save_state) { 268 if (save_state && (z_context->pc || (!z_context->reset && !z_context->busreq))) {
264 save_state = 0; 269 save_state = 0;
265 //advance Z80 core to the start of an instruction 270 //advance Z80 core to the start of an instruction
266 while (!z_context->pc) 271 while (!z_context->pc)
267 { 272 {
268 sync_z80(z_context, z_context->current_cycle + MCLKS_PER_Z80); 273 sync_z80(z_context, z_context->current_cycle + MCLKS_PER_Z80);
269 } 274 }
270 save_gst(gen, "savestate.gst", address); 275 save_gst(gen, "savestate.gst", address);
271 puts("Saved state to savestate.gst"); 276 puts("Saved state to savestate.gst");
277 } else if(save_state) {
278 context->sync_cycle = context->current_cycle + 1;
272 } 279 }
273 } 280 }
274 return context; 281 return context;
275 } 282 }
276 283
434 if (vdp_port & 0xE0) { 441 if (vdp_port & 0xE0) {
435 printf("machine freeze due to read from Z80 address %X\n", 0x7F00 | vdp_port); 442 printf("machine freeze due to read from Z80 address %X\n", 0x7F00 | vdp_port);
436 exit(1); 443 exit(1);
437 } 444 }
438 genesis_context * gen = context->system; 445 genesis_context * gen = context->system;
446 //VDP access goes over the 68K bus like a bank area access
447 //typical delay from bus arbitration
448 context->current_cycle += 3 * MCLKS_PER_Z80;
449 //TODO: add cycle for an access right after a previous one
450 //TODO: Below cycle time is an estimate based on the time between 68K !BG goes low and Z80 !MREQ goes high
451 // Needs a new logic analyzer capture to get the actual delay on the 68K side
452 gen->m68k->current_cycle += 8 * MCLKS_PER_68K;
453
454
439 vdp_port &= 0x1F; 455 vdp_port &= 0x1F;
440 uint16_t ret; 456 uint16_t ret;
441 if (vdp_port < 0x10) { 457 if (vdp_port < 0x10) {
442 //These probably won't currently interact well with the 68K accessing the VDP 458 //These probably won't currently interact well with the 68K accessing the VDP
443 vdp_run_context(gen->vdp, context->current_cycle); 459 vdp_run_context(gen->vdp, context->current_cycle);
681 context->current_cycle = context->sync_cycle; 697 context->current_cycle = context->sync_cycle;
682 } 698 }
683 //typical delay from bus arbitration 699 //typical delay from bus arbitration
684 context->current_cycle += 3 * MCLKS_PER_Z80; 700 context->current_cycle += 3 * MCLKS_PER_Z80;
685 //TODO: add cycle for an access right after a previous one 701 //TODO: add cycle for an access right after a previous one
702 //TODO: Below cycle time is an estimate based on the time between 68K !BG goes low and Z80 !MREQ goes high
703 // Needs a new logic analyzer capture to get the actual delay on the 68K side
704 gen->m68k->current_cycle += 8 * MCLKS_PER_68K;
686 705
687 location &= 0x7FFF; 706 location &= 0x7FFF;
688 if (context->mem_pointers[1]) { 707 if (context->mem_pointers[1]) {
689 return context->mem_pointers[1][location ^ 1]; 708 return context->mem_pointers[1][location ^ 1];
690 } 709 }
705 context->current_cycle = context->sync_cycle; 724 context->current_cycle = context->sync_cycle;
706 } 725 }
707 //typical delay from bus arbitration 726 //typical delay from bus arbitration
708 context->current_cycle += 3 * MCLKS_PER_Z80; 727 context->current_cycle += 3 * MCLKS_PER_Z80;
709 //TODO: add cycle for an access right after a previous one 728 //TODO: add cycle for an access right after a previous one
729 //TODO: Below cycle time is an estimate based on the time between 68K !BG goes low and Z80 !MREQ goes high
730 // Needs a new logic analyzer capture to get the actual delay on the 68K side
731 gen->m68k->current_cycle += 8 * MCLKS_PER_68K;
710 732
711 location &= 0x7FFF; 733 location &= 0x7FFF;
712 uint32_t address = context->bank_reg << 15 | location; 734 uint32_t address = context->bank_reg << 15 | location;
713 if (address >= 0xE00000) { 735 if (address >= 0xE00000) {
714 address &= 0xFFFF; 736 address &= 0xFFFF;