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comparison m68k_to_x86.c @ 146:5416a5c4628e

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Implement most of the "X" instructions
author Mike Pavone <pavone@retrodev.com>
date Mon, 31 Dec 2012 20:09:09 -0800
parents c4d10c2aaee2
children 3e68e517cc01
comparison
equal deleted inserted replaced
145:15b8dce19cf4 146:5416a5c4628e
2170 dst = setcc_r(dst, CC_S, FLAG_N); 2170 dst = setcc_r(dst, CC_S, FLAG_N);
2171 dst = setcc_r(dst, CC_O, FLAG_V); 2171 dst = setcc_r(dst, CC_O, FLAG_V);
2172 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); 2172 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
2173 dst = m68k_save_result(inst, dst, opts); 2173 dst = m68k_save_result(inst, dst, opts);
2174 break; 2174 break;
2175 //case M68K_ADDX: 2175 case M68K_ADDX:
2176 // break; 2176 dst = cycles(dst, BUS);
2177 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
2178 if (src_op.mode == MODE_REG_DIRECT) {
2179 if (dst_op.mode == MODE_REG_DIRECT) {
2180 dst = adc_rr(dst, src_op.base, dst_op.base, inst->extra.size);
2181 } else {
2182 dst = adc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
2183 }
2184 } else if (src_op.mode == MODE_REG_DISPLACE8) {
2185 dst = adc_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
2186 } else {
2187 if (dst_op.mode == MODE_REG_DIRECT) {
2188 dst = adc_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
2189 } else {
2190 dst = adc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
2191 }
2192 }
2193 dst = setcc_r(dst, CC_C, FLAG_C);
2194 dst = setcc_r(dst, CC_Z, FLAG_Z);
2195 dst = setcc_r(dst, CC_S, FLAG_N);
2196 dst = setcc_r(dst, CC_O, FLAG_V);
2197 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
2198 dst = m68k_save_result(inst, dst, opts);
2199 break;
2177 case M68K_AND: 2200 case M68K_AND:
2178 dst = cycles(dst, BUS); 2201 dst = cycles(dst, BUS);
2179 if (src_op.mode == MODE_REG_DIRECT) { 2202 if (src_op.mode == MODE_REG_DIRECT) {
2180 if (dst_op.mode == MODE_REG_DIRECT) { 2203 if (dst_op.mode == MODE_REG_DIRECT) {
2181 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size); 2204 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size);
2634 } 2657 }
2635 dst = setcc_r(dst, CC_Z, FLAG_Z); 2658 dst = setcc_r(dst, CC_Z, FLAG_Z);
2636 dst = setcc_r(dst, CC_S, FLAG_N); 2659 dst = setcc_r(dst, CC_S, FLAG_N);
2637 } 2660 }
2638 break; 2661 break;
2639 /*case M68K_ROXL: 2662 case M68K_ROXL:
2640 case M68K_ROXR:*/ 2663 case M68K_ROXR:
2664 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
2665 if (inst->src.addr_mode == MODE_UNUSED) {
2666 dst = cycles(dst, BUS);
2667 //Memory rotate
2668 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
2669 if (inst->op == M68K_ROXL) {
2670 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size);
2671 } else {
2672 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size);
2673 }
2674 dst = setcc_r(dst, CC_C, FLAG_C);
2675 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
2676 dst = setcc_r(dst, CC_Z, FLAG_Z);
2677 dst = setcc_r(dst, CC_S, FLAG_N);
2678 dst = m68k_save_result(inst, dst, opts);
2679 } else {
2680 if (src_op.mode == MODE_IMMED) {
2681 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2);
2682 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
2683 if (dst_op.mode == MODE_REG_DIRECT) {
2684 if (inst->op == M68K_ROXL) {
2685 dst = rol_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
2686 } else {
2687 dst = ror_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
2688 }
2689 } else {
2690 if (inst->op == M68K_ROXL) {
2691 dst = rol_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
2692 } else {
2693 dst = ror_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
2694 }
2695 }
2696 dst = setcc_r(dst, CC_C, FLAG_C);
2697 } else {
2698 if (src_op.mode == MODE_REG_DIRECT) {
2699 if (src_op.base != SCRATCH1) {
2700 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B);
2701 }
2702 } else {
2703 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
2704 }
2705 dst = and_ir(dst, 63, SCRATCH1, SZ_D);
2706 zero_off = dst+1;
2707 dst = jcc(dst, CC_NZ, dst+2);
2708 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
2709 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
2710 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B);
2711 norm_off = dst+1;
2712 dst = jcc(dst, CC_L, dst+2);
2713 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
2714 if (dst_op.mode == MODE_REG_DIRECT) {
2715 if (inst->op == M68K_ROXL) {
2716 dst = rol_ir(dst, 31, dst_op.base, inst->extra.size);
2717 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size);
2718 } else {
2719 dst = ror_ir(dst, 31, dst_op.base, inst->extra.size);
2720 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size);
2721 }
2722 } else {
2723 if (inst->op == M68K_ROXL) {
2724 dst = rol_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
2725 dst = rol_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
2726 } else {
2727 dst = ror_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
2728 dst = ror_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
2729 }
2730 }
2731 dst = sub_ir(dst, 32, SCRATCH1, SZ_B);
2732 *norm_off = dst - (norm_off+1);
2733 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
2734 if (dst_op.mode == MODE_REG_DIRECT) {
2735 if (inst->op == M68K_ROXL) {
2736 dst = rol_clr(dst, dst_op.base, inst->extra.size);
2737 } else {
2738 dst = ror_clr(dst, dst_op.base, inst->extra.size);
2739 }
2740 } else {
2741 if (inst->op == M68K_ROXL) {
2742 dst = rol_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
2743 } else {
2744 dst = ror_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
2745 }
2746 }
2747 dst = setcc_r(dst, CC_C, FLAG_C);
2748 end_off = dst + 1;
2749 dst = jmp(dst, dst+2);
2750 *zero_off = dst - (zero_off+1);
2751 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
2752 *end_off = dst - (end_off+1);
2753 }
2754 if (dst_op.mode == MODE_REG_DIRECT) {
2755 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
2756 } else {
2757 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
2758 }
2759 dst = setcc_r(dst, CC_Z, FLAG_Z);
2760 dst = setcc_r(dst, CC_S, FLAG_N);
2761 }
2762 break;
2641 case M68K_RTE: 2763 case M68K_RTE:
2642 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D); 2764 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
2643 dst = call(dst, (uint8_t *)m68k_read_long_scratch1); 2765 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
2644 dst = push_r(dst, SCRATCH1); 2766 dst = push_r(dst, SCRATCH1);
2645 dst = add_ir(dst, 4, opts->aregs[7], SZ_D); 2767 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
2684 dst = setcc_r(dst, CC_S, FLAG_N); 2806 dst = setcc_r(dst, CC_S, FLAG_N);
2685 dst = setcc_r(dst, CC_O, FLAG_V); 2807 dst = setcc_r(dst, CC_O, FLAG_V);
2686 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B); 2808 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
2687 dst = m68k_save_result(inst, dst, opts); 2809 dst = m68k_save_result(inst, dst, opts);
2688 break; 2810 break;
2689 //case M68K_SUBX: 2811 case M68K_SUBX:
2690 // break; 2812 dst = cycles(dst, BUS);
2813 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
2814 if (src_op.mode == MODE_REG_DIRECT) {
2815 if (dst_op.mode == MODE_REG_DIRECT) {
2816 dst = sbb_rr(dst, src_op.base, dst_op.base, inst->extra.size);
2817 } else {
2818 dst = sbb_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
2819 }
2820 } else if (src_op.mode == MODE_REG_DISPLACE8) {
2821 dst = sbb_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
2822 } else {
2823 if (dst_op.mode == MODE_REG_DIRECT) {
2824 dst = sbb_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
2825 } else {
2826 dst = sbb_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
2827 }
2828 }
2829 dst = setcc_r(dst, CC_C, FLAG_C);
2830 dst = setcc_r(dst, CC_Z, FLAG_Z);
2831 dst = setcc_r(dst, CC_S, FLAG_N);
2832 dst = setcc_r(dst, CC_O, FLAG_V);
2833 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
2834 dst = m68k_save_result(inst, dst, opts);
2835 break;
2691 case M68K_SWAP: 2836 case M68K_SWAP:
2692 dst = cycles(dst, BUS); 2837 dst = cycles(dst, BUS);
2693 if (src_op.mode == MODE_REG_DIRECT) { 2838 if (src_op.mode == MODE_REG_DIRECT) {
2694 dst = rol_ir(dst, 16, src_op.base, SZ_D); 2839 dst = rol_ir(dst, 16, src_op.base, SZ_D);
2695 } else{ 2840 } else{